Modern processors remove many artificial constraints on instruction ordering,permitting multiple instructions to be executed in parallel. As a result,only a fraction of all the instructions in a program trace determine the execution time of the program. Any effort to improve program performance is wasted when not applied to these critical instructions. Likewise, the remaining non-critical instructions may be delayed, to a point, without affecting performance. Depending on the program and microarchitecture, typically between a few percent and half of all dynamic instructions are critical. We propose and evaluate several hardware techniques to classify whether an instruction is critical or non-critical, and discuss related efforts at the same. We show that the criticality of dynamic instructions is correlated to the corresponding static instruction. We exploit this correlation to predict an instruction's criticality, in hardware, before it executes. We call this critical-path prediction. These predictions can be used anywhere that the processor must arbitrate between instructions for a limited resource. We demonstrate the utility of these predictions in several such applications, which we call critical-path aware optimizations: a processor with a limited-rate value-predictor, a clustered microarchitecture with inter-cluster communication delays, and a reduced-power microarchitecture with heterogeneous functional units and queues. We perform an offline analysis of the critical paths of programs to validate our findings and to quantify the degree of criticality of different instructions. Our findings lead us to propose a new multithreading architecture. Under our proposal, threads execute in parallel in a manner sensitive to the hardware implications of supporting multiple contexts, and also sensitive to the critical path issues. We use execution-driven simulation to evaluate the performance of all the processor designs which we propose.

Pre-2018 CSE ID: CS2004-0808