The advent of VHDL has brought about a number of VHDL simulators. Many translation schemes from domain specific languages to supposedly functionally equivalent VHDL have been developed as an approach to obtaining simulations. However, functionally equivalent VHDL can not be created for the general case, due to a theoretical limitation to this approach. It is a very subtle point and has thus been overlooked until now, but it is extremely important since it can cause incorrect siniulation, therefore making translations to VHDL an unsound simulation technique. In this paper, we introduce this fundamental limitation. In addition, we propose an alternative approach which strives for functionally equivalent simulation rather than functionally equivalent VHDL, while still taking advantage of VHDL simulators. Our method uses a novel time-shift transformation, also introduced in this paper, in conjunction with almost any translation scheme. The method makes correct simulations easily obtainable, thus bridging the gap to a truly sound and highly advantageous use of VHDL as a tool for simulating domain specific languages.

Many approaches have been developed to partition a system's behavioral description before a structural implementation is synthesized. We highlight the foundations and motivations for behavioral partitioning. We survey behavioral partitioning approaches, discussing abstraction levels, goals, major steps, and key assumptions in each.

The advent of VHDL has brought about a number of VHDL simulators. Many translation schemes from domain specific languages to supposedly equivalent VHDL have been developed as an approach to obtaining simulations. However, functionally equivalent VHDL can not be created for the general case, due to a theoretical limitation to this approach. It is a very subtle point and has thus been overlooked until now, but it is extremely important since it can cause incorrect simulation, therefore making translations to VHDL an unsound simulation technique. In this paper, we introduce this fundamental limitation. In addition, we propose an alternative approach which strives for functionally equivalent simulation rather than functionally equivalent VHDL, while still taking advantage of VHDL simulators. Our method uses a novel time-shift transformation, also introduced in this paper, in conjunction with almost any translation scheme. The method makes correct simulations easily obtainable, thus bridging the gap to a truly sound and highly advantageous use of VHDL as a tool for simulating domain specific languages.

SpecCharts is a new language intended for system level specification and synthesis. It is based on hierarchical state diagrams and VHDL, and posseses many constructs designed to facilitate ease of description. Since current requirements demand that a specification language be simulatable, an approach for simulating SpecCharts needed to be developed. Rather than taking on the major task of writing a new simulator, a translator from SpecCharts to VHDL was implemented. This permits making use of the advantages that accompany the standardization of VHDL, including use of powerful compilers and simulators, while maintaining the ability to describe systems concisely and perform system level synthesis steps. The SpecChart to VHDL translator must convert each SpecChart abstraction to functionally equivalent VHDL. This report describes each of those abstractions and their VHDL implementation. The system takes as input a SpecChart and outputs a VHDL file which, when compiled, is a simulatable entity that can be used as any other VHDL entity. Several examples display how the translator can be used to verify SpecChart models of systems, thus adding to SpecCharts capability as a system level specification language.

Embedded systems are small computers dedicated to performing a specific task and can be designed as simple as a temperature controller to a complex medical imaging system. Embedded systems are ubiquitous having diverse applications in areas such as personal devices, factory automation, military, and medicine. A particular need in many embedded systems is recognizing patterns from available information to achieve a goal, such as determining the kind of fruit passing on a conveyor belt. Pattern recognition is a mature field that studies algorithms for learning patterns in data. However, many embedded systems designers do not have the expertise in the pattern recognition domain which imposes a challenge on employing these algorithms in their system designs. In this study, we introduce a pattern recognition framework for embedded systems that enables developers to use an interactive environment, tutorial, and reference code to develop K-nearest neighbors classification algorithm, which is a robust model in pattern recognition. To validate benefits of the proposed framework, we conducted an experiment on 66 students to evaluate their performance in terms of the code quality and development speed when the framework is used, compared to when it is not. The results demonstrate a considerable gain in the development experience using our framework.

Executing a complex physical system model in real-time or faster has numerous applications in cyber-physical system. For instance, if a human lung model can be executed in real-time, the lung model can be used to test a ventilator in real-time. A complex physical system can often be captured with thousands of ordinary differential equations (ODEs). We introduce an approach to map the ODEs of a physical system to a custom network of processing elements on a field-programmable gate array (FPGA). A processing element (PE) is a light-weight processor that solves a subset of the ODEs. The custom interconnection of the processing elements is based on the data dependencies of the ODEs. The processing elements can execute in parallel and communicate with each other. To automate the design process, we developed a compilation tool to find a good mapping between the ODEs and the processing elements, and to generate synthesizable HDL (hardware description language) code for the entire design.

We first investigated a general purpose processing element that can solve any type of ODEs. The network of general PEs achieves 10-20x speedups against a single-threaded Intel I7-950 CPU, and 4x speedups against an Nvidia GTX 460 GPU. The network of general PEs also yields 2x speedups compared to a commercial high-level-synthesis tool. We further optimized our approach by building custom processing elements that can only solve certain type of ODEs. For homogeneous physical systems (contains only one or a few types ODEs), the network of custom PEs yields another 6x speedup compared to the network of general PEs, given comparable size. Finally, we introduced the network of heterogeneous PEs, where the network may contain both general PEs and different types of custom PEs. We developed an allocation and binding heuristic to explore the large design space. The network of heterogeneous PEs achieves 7x/6x speedup against the network of general PE/single-type custom PEs, and was on average 10x faster than the circuits generated by a high-level synthesis tool.

SpecCharts is a language intended for system level description and synthesis. It is based on hierarchical state diagrams, posseses many constructs designed to facilitate ease of system level descriptions, and is simulatable via a translator from SpecCharts to VHDL. To test the feasability of using the language, several examples were modeled using SpecCharts, were converted to VHDL, and simulated to verify correctness. The details of two of those examples are provided in this report.

Recent trends have led to parameterization of many computing components, such as parameterized processors, caches, FPGAs or networks-on-chip, as well as parameters in design tools such as optimization flags. Tuning parameterized systems to meet design goals like performance, energy, size, or power, has become harder due to the enormous design space created by such parameters and due to the large time required to evaluate each system configuration. Previous design space exploration approaches for parameterized systems have either focused on custom or randomized search heuristics. We map such design space exploration onto a statistical paradigm known as Design of Experiments, a paradigm under development since the 1920s that uses methodical experiment selection and sophisticated analysis to obtain maximum information using a minimum number of experiments. We introduce our DPG (Design-of-experiments Pareto-point Generator) method that performs flexible exploration by allowing the designer to provide information about the number and types of parameters, the approximate time to evaluate a configuration, and the total allowable exploration time. From that information, DPG automatically determines a custom set of experiments to best explore the design space within the allowable time. Such customized design-of-experiments-based exploration represents the unique contribution of this work. We show that DPG provides competitive results across different domains, without requiring the designer to have a detailed understanding of parameter impacts. We created a web-based DPG tool to support designers from various domains, which accepts information from the designer and generates experiments that the designer conducts (iteratively), and generates data and plots from the analysis, including Pareto-points. The effectiveness of the DoE paradigm for system tuning may have broad applicability for design automation.

This work is motivated by the observation that interest in computer science continues to grow, but failure rates in introductory programming courses ("CS1") have been concerning. Student frustration is a common source of dissatisfaction, attrition, and cheating in programming courses. A common cause of frustration is getting “stuck”, what we call struggling, on programming tasks, where students spend excessive time or make excessive attempts on a problem with little progress. We argue that early detection of struggle and cheating can help students, where instructors can provide early proper intervention. This dissertation addresses two problems: (1) Detecting and preventing struggle, and (2) Detecting and preventing cheating. The focus is mostly in CS1 but the work may apply to various programming courses. First, this work addresses the problem of how to identify struggle. We develop techniques and tools to measure and detect student struggle. A key novelty here is to identify programming errors that cause struggle rather than just errors that slightly annoy students, or common errors that may not cause struggle. This is important because some struggle is a normal part of learning to program.Second, this work addresses the problem of how to identify cheating. Many CS instructors use code similarity detection tools (such as Moss) to detect copied solutions shared among students in class. However, the code similarity detection approach is not effective to detect cheating when students submit unique solutions. Due to the accessibility and affordability of online “tutoring” services, a student can get a unique solution in a few minutes for about $1 (with a monthly subscription), even while the student is in a lab session. A key novelty here is to detect cheating that may not be detected by the code similarity approach. We propose techniques and tools to detect cheating. We show that our techniques and tools are powerful and able to identify and detect struggle and cheating in CS1 classes with good accuracy in a short time. To maximize the impact of our work, we plan to make our tools available to the CS community as free web tools. The techniques and tools can help improve education in CS1 and other programming courses.

A well-run introductory CS1 course is essential for all students within CS education. CS1 is necessary to keep students in the major and important to attract non-majors to the CS field. Unfortunately, there are many well-known issues that most CS1 courses have in common: high drop rates, low retention, high student stress, student struggle, academic dishonesty, and low grades. In this work, we aim to address these issues and seek to improve CS1 courses by focusing on weekly programming assignments. Our work introduces a different teaching approach from the traditional One Large Program (OLP) teaching approach, to a Many Small Programs (MSP) teaching approach. Instead of assigning students one large programming assignment to complete each week, the MSP approach involves assigning students multiple smaller programming assignments, for example 5-7 programs each week, instead. Such an approach has become more feasible with the advent of program auto-graders with immediate feedback to students, partial credit, and resubmit capabilities. In this dissertation, we discuss the conception of the MSP approach, provide insight into the process of transitioning from an OLP approach to an MSP approach, discuss various benefits that an MSP approach offers, discuss some pros and cons for using such an approach, present results from surveys and multiple analyses on various metrics related to an MSP approach, and discuss future use and improvements to the current MSP approach and tools used to analyze student interaction. This work shows that an MSP approach can lead to reduced student stress, can improve student grade performance, finds students making good use of the benefits an MSP approach offers, and shows that students are still well prepared for a CS2. Finally, we introduce a tool for instructors to upload their own MSP data sets to gain deep insight into their own students' behavior when using an MSP approach in their own classes.