UC Berkeley

As modern computing tasks increasingly involve processing vast amounts of data, therehas been a growing demand in recent years for power dissipation solutions that can deliver the high performance, speed, and energy efficiency required for data-intensive applications, such as machine learning and artificial intelligence (AI). Simultaneously, the discovery of ferroelectricity in a well-researched CMOS-compatible high-k dielectric material, HfO2, has led to a novel technology aimed at boosting device performance while minimizing power dissipation in electronics beyond fundamental limits, through the integration of ferroelectrics and the utilization of the negative capacitance (NC) effect.

This work presents the successful incorporation of a CMOS-compatible mixed-ferroic NCgate oxide, a 1.8-nm HfO2-ZrO2 superlattice (HZH), into bulk-Si MOSFETs, 90-nm SOI MOSFETs, and 30-nm extremely-thin SOI (ETSOI) MOSFETs. As the atomic-scale HfO2- based NC gate oxide is still a nascent technology, particular attention is given to acquiring a deeper understanding of the various device engineering challenges related to process integration and device performance for the superlattice. This gate stack exhibits a unique mixed order of co-existing ferroelectric and antiferroelectric phases, which has not been reported for such a low thickness before. The ferroic nature of the constituent layers enables an enhanced gate capacitance (Cgg) in our HZH n-MOSFETs (n-NCFETs) without frequency dispersion up to 40 GHz. When layered with an un-scavenged SiO2 interlayer (IL) of 8 A, our NC gate oxide counter-intuitively achieves a combined equivalent oxide thickness (EOT) of 7-7.5 A for all n-NCFETs, which is even thinner than the anticipated thickness of the SiO2 IL alone. This also represents over 2-A lowering of the EOT compared to the conventional high-k HfO2 dielectrics.

Furthermore, we confirm that the carrier transport in the n-NCFETs remains unaffected bythe aforementioned Cgg enhancement in our NC gate oxide, as no IL scavenging is utilized during the process. A record-high intrinsic transconductance (gmi) of 1.50 mS/m is achieved in 90-nm SOI n-NCFETs, along with a 14 % increase in ON-current compared to the HfO2 control, thanks to the lower EOT. The 90-nm n-NCFETs show enhanced PBTI reliability and approximately 20 % better end-of-life (EOL) characteristics. For energy-efficient cryogenic applications at 77 K, a 40 % increase in electron injection velocity (vinj) and a record gmi of 2.03 mS/m from 90-nm SOI n-NCFETs are observed, which is 19 % higher than the regular HfO2.

More importantly, to evaluate performance in the context of advanced devices with muchshorter channel lengths and to determine if the performance benets persist when the channel length is scaled down, replacement gate-last ETSOI n-NCFETs with Leff~30 nm are also developed and investigated. This advanced n-NCFETs exhibits an unprecedentedly high gmi of 2.11 mS/m, rivaling the performance of much shorter channel length (18 nm) commercial devices such as the GlobalFoundries 22FDX® FDSOI technology. Similar to our 90-nm SOI n-NCFETs technology, a 39 % increase in vinj with an unprecedented gmi of 2.87 mS/m in 30-nm ETSOI n-NCFETs is observed at 77 K for cryogenic applications. The successful integration of our NC gate stack into SOI transistors from 90 nm down to 30 nm demonstrates that (i) the vinj-Leff trend aligns with the established industry benchmark and (ii) the gmi-Leff tradeoff is steeper than that of 22FDX® FDSOI technology, highlighting the advantages of the low-EOT NC gate stack for the next-generation technology node.

The overall objective of this work is to pave the way for the ongoing advancement of sophisticatedMOSFETs combined with a novel CMOS-compatible NC gate oxide for leading-edge foundry CMOS technologies, which can be utilized for high-performance integrated circuit frameworks and data-intensive computing while reducing power consumption. The functional features of the NCFET with the atomic-scale mixed-ferroic HZH superlattice, considering its higher gate capacitance with (i) no need for IL scavenging, (ii) unaffected gate leakage, (iii) maintained carrier transport, and (iv) enhanced reliability, make it suitable for meeting the challenging modern computational requirements by bridging the gap between traditional logic, RF, and continued CMOS device scaling.