UC San Diego

In the contemporary era, sensors have become ubiquitous, permeating various facets of our daily lives and profoundly impacting society, industry, and the environment. The Internet of Things (IoT) and biosensors represent two broad categories of sensors. IoT sensors, equipped with wireless communication capabilities, facilitate real-time data collection and transmission from remote locations, enabling continuous monitoring and analysis of physical and environmental parameters. On the other hand, biosensors leverage biological recognition elements to detect specific analytes, ranging from biomolecules to pathogens, with high sensitivity and specificity. Integrated circuits are a primary link between all these applications. Analog front-ends are critical in accurately converting physical information into digital formats, facilitating further processing and analysis.From a circuit design standpoint, CMOS technology scaling poses fresh obstacles in analog design owing to the reduced supply voltage and transistors' reduced inherent voltage gain. These challenge analog circuit designers as they reduce the signal swing and attainable signal-to-noise ratio (SNR), leading to increased power consumption. Simultaneously, while device speed has increased in lower design nodes, its direct advantage for analog circuit design remains limited. This thesis introduces digital and technology-friendly circuit architectures through time-domain circuit techniques adept at minimizing area and power consumption while leveraging the accelerating transistor speeds. This work describes three examples of how this can be achieved, demonstrating the versatility of the approach by applying it to different sensors. First, a high-performance, low-power temperature sensor suitable for wireless IoT devices/RFID tags is described. The system utilized a mostly digital approach to achieve energy- efficient, sub-μW operation with a resistor-based temperature sensor. A sampled, incomplete- settling, switched-capacitor-based Wheatstone bridge was read out using a digital frequency- locked loop (DFLL) while harnessing the quasi-periodic limit cycles to reduce in-band noise. Implemented in a 65 nm CMOS process, it consumed 310 nW and achieved 9.8 mK resolution in a 10 ms conversion time. This resulted in a 297 fJ·K2 figure-of-merit (FoM) and low energy (3.1 nJ/meas.). Next, a 16×20 CMOS biosensor array-based on electrochemical impedance spectroscopy (EIS) is presented. This high-density system implemented a polar-mode detection scheme with phase-only EIS measurement over a 5 kHz – 1 MHz frequency range. The design featured predominantly digital readout circuitry, ensuring scalability with technology, along with a load- compensated TIA at the front, all within a 140×140 μm2 pixel. The architecture enabled in-pixel digitization and accumulation, which increases the SNR by 10 dB for each 10× increase in readout time. Implemented in a 180 nm CMOS process, the 3×4 mm2 chip achieved state-of-the-art performance with an rms phase error of 0.035% at 100 kHz through a duty-cycle insensitive phase detector. Lastly, an 8-channel, in-pixel 2nd-order ΔΣ ADC is presented for the direct digitization of neural recording signals in a closed-loop neuromodulation system. This paper addresses the stimulation artifact recovery time in voltage-controlled oscillator (VCO)-based quantizers with a fast-recovery, overrange-detecting phase quantizer. The ADC incorporates a pseudo virtual ground feedforwarding (PVG FF) technique and a complementary input Gm-C filter with per-pixel decimation. It supports four recording modes covering 2.5–20 kSps through a power-efficient, bandwidth-scalable continuous time ΔΣ modulator. Fabricated in a 180-nm CMOS process, this 300×300 μm2 ADC achieves the fastest (0.05-0.4 ms) stimulation artifact recovery time, enabling in-stimulation recording. Recording with artifact tolerance was demonstrated through an in vivo whisker barrel rat experiment.