UCLA

Conventional analog layout design relies heavily on full-custom design methodologies, which demands significant expertise and labor-intensive manual work. On the other hand, digital layout design achieves efficient automation by leveraging standard cells and mature place and route (PnR) tools. Inspired by digital standard cells, prior research introduced ”analogstandard cells”, called ”stem cells”, that are abuttable and can be recognized and used by digital PnR tools. But the stem cells have limited transistor parameter range and low area efficiency. In this thesis, we presents an improved design of abuttable analog cells, called Acells, for both transistors and passive devices. Acells are abuttable with digital standard cells and other Acells in all directions, and thus compatible with digital PnR tools. Using improved design methodologies, Acells have higher area efficiency and broadened parameter range. The generation of Acells is automated, and experiments show that their average area ratio compared to corresponding parameterized cells (Pcells) is 1.49 in 65nm technology and 1.3 in 28nm. We verify the design flow and do the case study using multiple analog and mixed-signal (AMS) circuits in 28nm and 65nm. The experiments show that Acell-based layouts achieve comparable performance and area to Pcell-based layouts, but with significant higher design efficiency.