UC Berkeley

Wireless technology is facing several important trends. Growing demand for throughput and capacity on one end, and the ever-increasing push towards ubiquitous connectivity on the other end, have strained current systems and standards. Energy efficiency remains a critical issue for all of these applications, and has become an important challenge to balance in face of higher performance requirements. New applications and standards require radio systems that can provide multi-Gb/s wireless links on mobile devices with minimal impact on battery life. On the other side, connectivity is projected to move from people to objects in the realm of Internet of Things (IoT), scaling to trillions of radios in the next decade. This work addresses capacity and connectivity demands for next-generation radios.

In the area of IoT, ultra-low power highly miniaturized smart radios that can provide unique IP addresses and their locations are an important requirement of the system. In this context, battery-less radios are the ultimate frontier in scaling the size and cost of a communication node. However, there are several key challenges that still need to be addressed in this area. Cost (dominated by antenna board and interface), number of readable transponders (and latency in doing so), data-rate capacity, localization and miniaturization are the issues faced by today's designers. To overcome these challenges, a new approach for miniaturization of smart passive radios is proposed. We demonstrate a single-chip 24GHz/60GHz radio implemented in 65nm CMOS. This millimeter-sized chip radio is fully self-sufficient with no pads or any external components (e.g. power supply).

In order to address capacity demands, the 60GHz band with 7GHz of unlicensed spectrum provides a unique opportunity. A shift to mm-wave systems also enables beamforming by phased-array systems, which is critical in interfacing with the proposed passive radio. How- ever, integration, energy efficiency, and system cost remain to be obstacles in this space. In the second part of this thesis, we propose new system and circuit solutions and strategies for this application, and demonstrate an example design with a 4-element 60GHz phased-array receiver in 65nm CMOS. Energy and area efficiency is achieved by utilizing a baseband phase shifting architecture, holistic impedance optimization, and lumped- element based design. Finally, to enable scalability to larger arrays and to support hybrid RF/IF phase shifting, a lumped-element architecture for 60GHz phase-shifters is proposed and is shown to achieve low loss in a compact form factor.