UC Berkeley

The ever-growing demand for increased wireless data capacity has driven the carrier frequency of transceivers towards millimeter-wave and sub-THz frequencies, where a modest fractional bandwidth presents the opportunity to exploit a large available absolute bandwidth. However, the severe path loss at such frequencies necessitates the deployment of massive arrays. To effectively scale to such arrays, the energy efficiency of the transceiver element, as well as the local oscillator (LO) generation and distribution within the array, must be maximized. Moreover, minimizing costs and maximizing on-chip integration furthers the need for implementation in CMOS technologies.

This dissertation addresses the design and implementation of wideband and energy-efficient CMOS receivers operating at D-band (140 GHz) and G-band (200 GHz) frequencies, as well as the integrated low-power LO generation, synthesis, and distribution circuits required for down-conversion. First, the design of a packaged D-band four-element receiver array for digital beamforming is presented. Fabricated in 28nm CMOS, the receiver array operated in single-element configuration demonstrates a 16 Gb/s wireless downlink with one of the lowest DC power consumption per element levels and competitive energy efficiency of 5.1 pJ/bit compared to other wireless downlinks in CMOS. A 24 Gb/s wireless downlink is supported with all four elements combined.

Next, the performance evaluation of sub-THz G-band receivers is presented. The designs of several key receiver and LO path building blocks are detailed. An ultra-compact, fully-differential LNA demonstrates one of the highest fractional bandwidths, lowest noise figures, and wideband input matching compared to other works in CMOS. These blocks are integrated in the design of both LNA-first and mixer-first wideband receivers implemented in 16nm FinFET. Simulated performance compared to other works in CMOS predict competitive performance while consuming significantly lower DC power, projecting sub-2 pJ/bit energy efficiencies and suitability for use in next-generation high-capacity receiver arrays.