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Single-Chip 64- and 256-Element Wafer-Scale Phased Arrays and Communication Circuits in Advanced SiGe and CMOS Technologies

  • Author(s): Zihir, Samet
  • Advisor(s): Rebeiz, Gabriel M.
  • et al.
Abstract

The development of millimeter-wave phased arrays has been mostly based on silicon RFIC chips containing 8-16 channels and connected to antennas on organic printed circuit boards, or on wafer-scale phased arrays with on-chip antennas. Extending the

wafer-scale array to a large number of elements results in an un-surmountable challenge, mainly that the phased-array chip may be much larger than a full reticle (approximately 22x22 mm2), and this is not allowed using standard integrated circuit design and layout rules. This dissertation focuses on the implementation of wafer-scale phased array with 64- and 256-elements using sub-reticle stitching techniques. An implementation of the largest single-chip wafer-scale phased-array ever built is demonstrated. The measured EIRP is 38 dBm and 45 dBm, with measured half-power beamwidth of 12.5 and 6 at 61 GHz for the 64- and 256-element phased arrays, respectively. This work allows the construction of large-scale (1000+ elements) phased-array systems, either on a single wafer or by assembling several of these chips together on a low cost board.

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