The von Neumann bottleneck has been growing narrower over the years, as CPU speed and memory have been increasing much faster than the bandwidth between them can accommodate. One promising approach to circumvent this problem is logic-in-memory computing, where computation is performed in the memory itself, significantly reducing traffic between the CPU and the memory subsystem. The most practical implementation of logic-in-memory utilizes electronic devices that can perform both storage and logic while being monolithically integrated into existing CMOS technology. A very prominent example of such a device is the memristor a two-terminal memory devices with high endurance, low power consumption, and proven scalability down to 10 nm. Memristors are now actively investigated for non-volatile memory applications and energy-efficient hardware implementations of artificial neural networks. Recently, a novel logic-in-memory approach implementing material implication logic with memristors was proposed by Hewlett Packard, providing a potential new way forward for opening the von Neumann bottleneck.

The objective of this dissertation is to advance of the state of the art for material implication logic through three research goals. Our first goal was to develop a fabrication pathway for monolithical vertical integration of memristors in order to implement 3D memories. This allows us to experimentally test logic-in-memory systems. Our second goal was to determine memristor device and circuit constraints for implementing material implication logic and explore circuit and device level solutions to increase robustness of operation. Our final goal was to combine these two efforts together and demonstrate reliable material implication logic in vertically stacked memristors. To this end, we fabricated and successfully tested monolithically stacked memristive structures implemented with TiO2-based memristors. We also developed an optimized circuit configuration able to perform material implication with maximum tolerance to device variations. This allowed us to demonstrate, for the first time, hundreds of successful three-dimensional data manipulation cycles using material implication. An inter-layer NAND gate with the inputs and output in different device layers was implemented with 94% yield. This high yield demonstrates the potential for using the inter-layer stateful logic gates in larger circuits for in-memory logic. This implementation also opens the way through aggressive scaling to achieve one of the Feynman Grand Challenges - the construction of a functional nano-scale 8-bit adder in 50x50x50nm for which a circuit implementation is proposed.