To implement chip design on a satisfactory target architecture, more architecture exploration should be done at higher levels of abstraction, in the earliest design stages. Using the SpecC language, an executable system level specification language, architecture exploration can be processed easily and smoothly. A SpecC methodology of system level architecture exploration is introduced within this paper to illustrate this process. The design of a JPEG encoder is used as an example to illustrate the system level architecture exploration methodology.

This report describes the design of a JBIG encoder, based on the ITU-T Recommendation T.82, using the SpecC system level design methodology being developed at CAD Lab, UC Irvine. We begin with an executable specification in SpecC, and explore design alternatives for the system architecture, and refine the specification into a final communication model where the communication protocols between the system components are defined. In this report, we document the different design stages undergone, and also the results in the process.

This report describes the design of a JPEG encoder. The project is a result of a course "System Tools" at Information and Computer Science Department, UC Irvine. The abstract executable specification SpecC is first developed based on a public domain C implementation. Software and hardware estimation is then performed based on which a datapath architecture is selected and RTL code is implemented. Finally, to explore the method of implementing a gate level model, part of the JPEG encoder is refined to the gate level.