When synthesizing a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operation into control steps. Prior to scheduling, most existing behavioral synthesis systems either require the designer to specify the clock cycle explicitly or require that the delays of the operators used in the design be specified in multiples of a clock cycle. A bad choice of the clock cycle could adversely affect the performance of the synthesized design. We present mathematical proofs of setting clock cycle length with zero clock slack and an algorithm for estimating the system clock based on a clock slack minimization criteria. This algorithm guarantee the minimum average clock slack.

HLS scheduling algorithms can not be applied on system-level synthesis due to the following problems:

- The control-step is not available at system-level.

- Mixed concurrent and exclusive execution flows

- Synchronization among objects scheduled

- Execution time of objects scheduled may not be determined until run-time.

In this paper, we present a data-structure to specify the Input for system-level scheduling, and a system-level timing-constrained scheduling algorithm. Static scheduling, which has no OS overhead and better system WCET, is used. The algorithm presented can obtain near-optimal solutions within acceptable and predictable CPU time.

A generic binding model which can provide complete information for binding task is presented in this paper. With information provided by this model, people can do interconnection optimization concurrently with operation and variable binding, as well as find better combination of FUs. Our method is not only much faster but also can obtain better or competitive binding than complex previous works.

This report describes how to use SpecC System-Level Scheduling (SLS) tools, as well as definitions of SLS tools, restrictions of curren release, and how to read the redefined design generated by SLS tools.

For quick start, two simplified SLS tools provide basic scheduling functions. However, due to various situations in real designs, we suggest advance designers use combination of all SLS tools to utilize all features provided by SLS tools to obtain better results.

A new binding model which can formulate any architectures is presented in this paper. Several simple algorithms which employ this model are proposed to demonstrate the performance on this model. Experimental results show that these algorithms though are simple yet can obtain better results than previous complex algorithms. In addition, exchanging sources of functional units and sharing functional units, which can improve synthesized results by way of reducing MUX inputs required, are also discussed in this paper.

This report contains information about software performance of Toshiba TLCS-R3900 RISC processor evaluated by a software estimation technique proposed by J. Gong et. al. This technique decomposes the program into basic block then evaluates total execution time by analysis execution flow. The execution time of basic block is computed by compiling subprogram into generic instructions then mapping to real instruction. In addition, we analyze the pipeline stall phenomenon for TLCS-R3900. A processor profile is proposed to count the effects. Based on this generic estimation model, our estimator can produce accurate estimation without large computation time and precious resource, such as compilers or simulators for each processor.

HLS scheduling algorithms can not be applied on system-level synthesis due to the following problems.

- The clock is no longer able to align the scheduled objects at system-level

- Combined concurrent and exclusive execution flows

- Synchronization precedences among the scheduled objects

- Execution time of the scheduled objects may not be determined until run-time.

In this paper, we present an extended task graph to capture the system-level scheduling problems. We define the system-level time-constraint scheduling problems based on the extended task graph, and a scheduling algorithm is presented. Static scheduling, which can have less OS overhead and better system WCET, is used. The algorithm can obtain good solutions within acceptable and predictable CPU time.

An important decision in synthesizing a hardware implementation from a behavioral description is selecting the clock period to schedule the datapath operations into control steps. Prior to scheduling, most existing behavioral synthesis systems either require the designer to specify the clock period explicitly or require that the delays of the operators used in the design be specified in multiples of the clock period. An unfavorable choice of the clock period could result in operations being idle for a large portion of the clock period, and consequently, affect the performance of the synthesized design. In this paper, we demonstrate the effect of clock slack on the performance of designs and present an algorithm to find a slack-minimal clock period. We prove the optimality of our method and apply it to several examples to demonstrate its effectiveness in maximizing design performance.

In this report, we describe the specify-explore-refine (SER) co-design methodology for design of embedded systems. We describe the necessary design steps in order to map an abstract specification of the system to the final implementation model. We propose a co-design tool based on our co-design methodology. We also present a graphical user interface for the proposed co-design tool.