Verification for hardware security has become increasingly important in recent years as our infrastructure is heavily dependent on electronic systems. Traditional verification methods and metrics attempt to answer the question: does my design correctly perform the intended specified functionality? The question this dissertation addresses is: does my design perform malicious functionality in addition to the intended functionality? Malicious functionality inserted into a chip is called a Hardware Trojan.

This work is devoted to developing both new threat models and detection methodologies for a less studied but extremely stealthy class of Trojan: Trojans which do not rely on rare triggering conditions to stay hidden, but instead only alter the logic functions of design signals which have unspecified behavior, meaning the Trojan never violates the design specification.

The main contributions of this work are 1) precise definitions for dangerous unspecified functionality in terms of information leakage and several methods to identify such functionality, 2) satisfiability-based formal methods to test potentially dangerous unspecified functionality for the existence of Trojans, and 3) numerous examples of how the proposed Trojans can completely undermine system security if inserted in on-chip bus systems, communication controllers, and encryption IP.

Modern test programs for post-silicon testing include a large number of test measurements applied in multiple settings such as different temperatures, supply voltages, and operation modes to meet the demanding quality requirements of the products. In addition to the pass/fail results of each test item, there exist multiple types of correlations in the huge amount of production test data. Identifying and modeling the hidden correlations in the test data could help screen test escapes, which are chips that pass all test items but fail in system-level application.

This thesis focuses on developing revealing features and machine learning algorithms for classifying test escapes based on production test data. In terms of feature engineering, three types of feature sets that represent different aspects of how a chip deviates from the normal population are proposed. In addition, a linear transformation that compacts the critical information for feature reduction and a collection of nonlinear transformations that reveal additional abnormalities of the test escapes are proposed to effectively expose the test escapes as outliers in certain perspectives. We have also developed frameworks exploiting state-of-the-art machine learning algorithms including a support vector machine (SVM), a cascade of AdaBoost classifiers, and an artificial neural network.

The manufacturing test process for a modern integrated circuit encounters excessively long test time and produces huge amount of test data. There is valuable information hidden in the test data about the device under test (DUT), far more than the binary go/no-go classification. Exploring the hidden correlations and patterns in the test data allows better understanding of the DUT and therefore leads to broad applications, such as test cost reduction and silicon characterization for discovering parametric variations and weak links

in the manufacturing process.

The first part of this dissertation proposes a methodology with supporting statistical learning algorithms for test time and cost reduction through exploiting both spatial and inter-test-item correlations in the test data. The proposed algorithm identifies inter-test-item correlations for removing costly and unnecessary test items from a test program. An integrated method further reduces test time by taking into account spatial correlations of test data across a wafer and maximizing the number of test items whose values can be predicted without measurement. A case study of a high-volume industrial device demonstrates that some test items can be identified for removal from the test program without compromising test quality and shows the significant reduction of test time.

In the second part of the dissertation, a framework for characterizing systematic variations and failures through exploring the hidden patterns of test data from multiple test stages is developed. The framework provides prediction of process variations with a fine resolution based on a limited number of probed process parameters, and extracts spatial patterns from both process parameters and production tests. A template matching technique exploits these spatial patterns to discover connections between process variations and failures detected by production tests. Experimental results demonstrate that the proposed framework reveals comprehensible and significant correlations in an industrial test dataset.

The third part of the dissertation describes a software toolbox dedicated to test data analytics developed in the course of this research. The toolbox provides flexible and scalable functions for parsing, processing, learning and display test data. The toolbox, which is released for non-commercial use, also provides examples and application programming interface for test data analysis.

Affordable consumer drones have made capturing aerial footage more convenient and accessible. However, shooting cinematic motion videos using a drone is challenging because it requires users to analyze dynamic scenarios while operating the controller.

In this thesis, our task is to develop an autonomous drone cinematography system to capture cinematic videos of human motion. We understand the system's filming performance to be influenced by three key components: 1) video quality metric, which measures the aesthetic quality -- the angle, the distance, the image composition -- of the captured video, 2) visual feature, which encapsulates the visual elements that influence the filming style, and 3) camera planning, which is a decision-making model that predicts the next best movement. By analyzing these three components, we designed two autonomous drone cinematography systems using both heuristic-based methods and learning-based methods.

For the first system, we designed an Autonomous CinemaTography system -- "ACT" by proposing a viewpoint quality metric focusing on the visibility of the 3D human skeleton of the subject. We expanded the application of human motion analysis and simplified manual control by assisting viewpoint selection using a through-the-lens method. For the second system, we designed an imitation-based system that learns the artistic intention of the cameramen through watching professional aerial videos. We designed a camera planner that analyzes the video contents and previous camera motion to predict future camera motion. Furthermore, we propose a planning framework, which can imitate a filming style by ``seeing" only one single demonstration video of such style. We named it ``one-shot imitation filming." To the best of our knowledge, this is the first work that extends imitation learning to autonomous filming. Experimental results in both simulation and field test exhibit significant improvements over existing techniques and our approach managed to help inexperienced pilots capture cinematic videos.

Abstract

Design and Automation for High Fidelity Flexible Hybrid Electronics

by Leilai Shao

Flexible electronics is emerging as an alternative to conventional silicon electronics for appli- cations such as wearable sensors, artificial skin, medical patches, bendable displays, foldable solar cells and disposable RFID tags. Combining FE with thinned silicon chips, known as flexi- ble hybrid electronics (FHE), can take advantages of both low-cost printed electronics and high performance silicon chips. There exist several challenges before FHE can be broadly employed for next-generation wearable and IoT products. Due to material properties, TFTs are usually mono-type, either only p- or only n-type, devices. Existing CMOS design methodologies for silicon electronics, therefore, cannot be directly applied for designing flexible electronics. To address these challenges, a trustworthy TFT compact model and process design kit (PDK) is needed to facilitate simulations and design explorations.

In the first part, we developed the compact model for thin film transistors, which has been validated extensively with carbon nanotube (CNT), organic and indium gallium oxide (IGZO) devices. The developed model has been implemented in Verilog-A, which can perform co- simulations with silicon chips. With the developed model, we further built the FHE-PDK for flexible thin-film transistors (TFTs) and passive elements, including technology files for design rule checking (DRC), layout versus schematic (LVS) and layout parasitics extraction (LPE), as well as SPICE-compatible models. Wafer scale measurements are used to validate our SPICE models and design rules are derived accordingly to assure a satisfactory yield. With the developed FHE-PDK, we further built the robust Pseudo-CMOS cell library to address the mono-type design challenges.

In the second part, we focused on addressing FHE system design issues. Specifically, motion noises in the flex-rigid interface and sensor defects in large area sensing system. We proposed the ”active electrode” (with a thickness ≤2 um), which integrates the electrode with a thin-film transistor (TFT) based amplifier, to effectively suppress motion artifacts. The fab- ricated ultra-thin amplifier can achieve a gain of 32 dB at 20 kHz. The simulation results indicate that the active electrode can significantly improve the signal quality under motion noise (achieving ≥30 dB improvement in signal-to-noise ratio (SNR)) and boost classification accuracy by ≥19% for atrial fibrillation (AF) detection. We further study robustness issue of ultra-thin flexible electronics caused by inadequate device yield, reliability and stability which is inevitable due to the low temperature requirement for fabrication and the large-area nature of flexible sensing arrays. As signals sensed by body sensor arrays exhibit sparse statistical char- acteristics, we present a system design solution to leverage the sparse nature via compressed sensing (CS) which can ensure system robustness without relying on highly reliable devices. Specifically, we implement a flexible CS encoder together with the sensor array using carbon- nanotube-based flexible TFTs and decode the compressed signal in the silicon side. Our quan- titative analysis, validated through two case studies: temperature imaging and tactile-sensor based object recognition, showed that the proposed robust sensing schema can accommodate up to 20% sparse defects (device defects or transient errors).