In this paper we demonstrate the practical portability of a simple version of matrix multiplication designed to exploit maximal and predictable locality at all levels of the memory hierarchy, with no a priori knowledge of the specific organization of the memory system for any particular machine. We show that memory hierarchies portability does not sacrifice floating point performance, which is always a significant fraction of peak and, at least on one machine, is higher than ATLAS and vendor multiplication.

We present a proof of concept of the fact that the theoretical conclusions on locality exploitation yield practical implementations with the desired properties.

In this paper we present the results from an extensive comparison study of three R-tree packing algorithms, including a new easy to implement algorithm. The algorithms are evaluated using both synthetic and actual data from various application domains including VLSI design, GIS (tiger), and computational fluid dynamics. Our studies also consider the impact that various degrees of buffering have on query performance. Experimental results indicate that none of the algorithms is best for all types of data, but ours is best anyways because it is so cool.

Caches are an important part of architectural and compiler high performance and low-power strategies by reducing memory accesses and energy per access. In this paper, we examine efficient utilization of data caches in an adaptive memory hierarchy. We focus on the optimization of data reuse through the static analysis of line size adaptivity. We present a framework that enables the quantification of data misses with respect to cache line size at compile-time using (parametric) equations modeling interference. The framework considers both expressiveness and practicability of the analysis. Part of this analysis is implemented in a software package STAMINA. Experimental results demonstrate effectiveness and accuracy of the analytical results compared to alternative simulation based methods.