Donald Bren School of Information and Computer Sciences

Caches are an important part of architectural and compiler high performance and low-power strategies by reducing memory accesses and energy per access. In this paper, we examine efficient utilization of data caches in an adaptive memory hierarchy. We focus on the optimization of data reuse through the static analysis of line size adaptivity. We present a framework that enables the quantification of data misses with respect to cache line size at compile-time using (parametric) equations modeling interference. The framework considers both expressiveness and practicability of the analysis. Part of this analysis is implemented in a software package STAMINA. Experimental results demonstrate effectiveness and accuracy of the analytical results compared to alternative simulation based methods.