Through Silicon vias (TSVs) have become the basis for 3D integration packaging systems such as Samsung’s High-Bandwidth Memory (HBM) and 3D Hybrid Cube (H-Cube) DRAM, TSMC’s Chip on Wafer on Substrate(CoWoS) packaging, and others. They enable power delivery, signal transmission, and heat dissipation by passing through several chips stacked on top of each other. They also serve a similar purpose in wafer scale systems (WSS). As an aim to replace PCB with Silicon, a WSS known as Silicon Interconnect Fabric (Si-IF) is being developed for heterogeneous integration, high power applications, and high interconnect density.For power delivery, the interconnections that pass through the wafer are fabricated named as Through wafer Vias (TWVs).
TWVs involve a complex fabrication process that includes etching the via, deposition of various layers like seed and barrier layer, followed by electroplating of copper. Challenges do arise in etching large diameters of vias on a wafer, choosing the appropriate geometry for uniform seed layer deposition by Denton and Ulvac sputter machines, and achieving defect-free electroplating.
In this thesis, we first used the laser drilling process to etch the via, as it provides flexibility with the via geometry, a mask-free process, and lower fabrication costs than other processes. We optimized the laser drilling parameters and later sputtered and electroplated the vias with Copper. Finally, we did a comparative study between two sputter machines for achieving a good quality seed layer and also proposed the optimized laser parameters that helps in obtaining defect-free plating.
