Until 2003, the semiconductor industry followed Dennard scaling rules to improve complementary metal-oxide-semiconductor (CMOS) transistor performance. However, performance gains with further reductions in transistor gate length are limited by physical effects that do not scale commensurately with device dimensions: short-channel effects (SCE) due to gate-leakage-limited gate-oxide thickness scaling, channel mobility degradation due to enhanced vertical electric fields, increased parasitic resistances due to reductions in source/drain (S/D) contact area, and increased variability in transistor performance due to random dopant fluctuation (RDF) effects and gate work function variations (WFV). These emerging scaling issues, together with increased process complexity and cost, pose severe challenges to maintaining the exponential scaling of transistor dimensions. This dissertation discusses the benefits of oxygen-insertion (OI) technology, a CMOS performance booster, for overcoming these challenges.

The benefit of OI technology to mitigate the increase in sheet resistance ($R_{sh}$) with decreasing junction depth ($X_J$) for ultra-shallow-junctions (USJs) relevant for deep-sub-micron planar CMOS transistors is assessed through the fabrication of $R_{sh}$ test structures, electrical characterization, and technology computer-aided design (TCAD) simulations. Experimental and secondary ion mass spectroscopy (SIMS) analyses indicate that OI technology can facilitate low-resistivity USJ formation by reducing $R_{sh}$ and $X_J$ due to retarded transient-enhanced-diffusion (TED) effects and enhanced dopant retention during post-implantation thermal annealing. It is also shown that a low-temperature-oxide (LTO) capping can increase $R_{sh}$ unfavorably due to lower dopant activation levels, which can be alleviated by OI technology.

This dissertation extends the evaluation of OI technology to advanced FinFET technology, targeting 7/8-nm low power technology node. A bulk-Si FinFET design comprising a super-steep retrograde (SSR) fin channel doping profile achievable with OI technology is studied by three-dimensional (3-D) TCAD simulations. As compared with the conventional bulk-Si (control) FinFET design with a heavily-doped fin channel doping profile, SSR FinFETs can achieve higher $I_{on}/I_{off}$ ratios and reduce the sensitivity of device performance to variations due to the lightly doped fin channel. As compared with the SOI FinFET design, SSR FinFETs can achieve similarly low $V_{DD,min}$ for 6T-SRAM cell yield estimation. Both SSR and SOI design can provide for as much as 100 mV reduction in $V_{DD,min}$ compared with the control FinFET design. Overall, the SSR FinFET design that can be achieved with OI technology is demonstrated to be a cheaper alternative to the SOI FinFET technology for extending CMOS scaling beyond the 10-nm node.

Finally, this dissertation investigates the benefits of OI technology for reducing the Schottky barrier height ($\Phi_{Bp}$) of a Pt/Ti/p-type Si metal-semiconductor (M/S) contact, which can be expected to help reduce the specific contact resistivity for a p-type silicon contact. Electrical measurements of back-to-back Schottky diodes, SIMS, and X-ray photoelectron spectroscopy (XPS) show that the reduction in $\Phi_{Bp}$ is associated with enhanced Ti 2p and Si 2p core energy level shifts. OI technology is shown to favor low-$\Phi_{Bp}$ Pt monosilicide formation during forming gas anneal (FGA) by suppressing the grain boundary diffusion of Pt atoms into the crystalline Si substrate.

Continued planar bulk MOSFET scaling is becoming increasingly difficult due to increased random variation in transistor performance with decreasing gate length, and thereby scaling of SRAM using minimum-size transistors is further challenging. This dissertation will discuss various advanced MOSFET designs and their benefits for extending density and voltage scaling of static memory (SRAM) arrays. Using threedimensional (3-D) process and design simulations, transistor designs are optimized. Then, using an analytical compact model calibrated to the simulated transistor current-vs.-voltage characteristics, the performance and yield of six-transistor (6-T) SRAM cells are estimated. For a given cell area, fully depleted silicon-on-insulator (FD-SOI) MOSFET technology is projected to provide for significantly improved yield across a wide range of operating voltages, as compared with conventional planar bulk CMOS technology. Quasi-Planar (QP) bulk silicon MOSFETs are a lower-cost alternative and also can provide for improved SRAM yield. A more printable "notchless" QP bulk SRAM cell layout is proposed to reduce lithographic variations, and is projected to achieve six-sigma yield (required for terabit-scale SRAM arrays) with a minimum operating voltage below 1 Volt.

In the past few decades, the central theme of the electronics industry is to increase the transistor density by reducing the transistor area, as required by the Moore's Law. The paradigm shift from the planar CMOS technology to the FinFET technology sustains this area scaling trend into sub-20nm era. The enhancement in the transistor electrostatics in the FinFET enables further scaling of the gate length and hence the contacted poly pitch (CPP). Meanwhile, the quest for area scaling also comes from the width (or fin pitch) and height dimensions. By reducing the fin pitch and increasing the fin height, the current density of the FinFET can be improved. Consequently, circuit designers can use fewer fins to meet the same current requirement and save area simultaneously, a scheme commonly referred to as "fin-depopulation." However, the aforementioned approaches start to show diminishing returns and meet excessive fabrication challenges. To further improve the current density and reduce the area, novel channel materials with high mobility (e.g., SiGe) and/or new structures with even better electrostatics (e.g., Inserted-oxide FinFET (iFinFET), Gate-All-Around FET, Nanosheet FET) are projected to be used in the future.

In the first part of the talk, the performance of a p-channel FinFET comprising a heterogeneous silicon (Si) and silicon-germanium (Si_{0.9}Ge_{0.1}) channel region is evaluated using 3-D TCAD simulations. It is shown that the hetero-channel design provides for larger current density while maintaining comparable electrostatic integrity as the conventional Si FinFET design due to the valence band (VB) offset between SiGe and Si.

Secondly, a scheme for controllably adjusting transistor drive strength in iFinFET technology is proposed, to enable cell ratio tuning for a minimally sized six-transistor SRAM (6-T Static Random Access Memory) cell. It is demonstrated, via 3-D TCAD simulation, that this scheme can reduce the minimum cell operating voltage (V_{min}) and facilitate further cell area scaling.

Lastly, as the transistor area continues to shrink, self-heating effects of these small-geometry transistors have been of great concern as it limits the electrical performance and degrades the reliability of transistors. It is important to understand how self-heating may be for these new transistor structures as compared to FinFETs. The performance of advanced transistor structures (i.e., FinFET, Gate-All-Around FET, and Nanosheet FET) is simulated and compared under the constraints of the self-heating. An optimization guideline for nanosheet FETs is also proposed based on the study of various design parameters on the self-heating effects.

The semiconductor industry is now struggling with an integrated-circuit “chip” power density crisis due to the non-scalability of the thermal voltage (kBT/q), which sets the minimum subthreshold swing (SS) of a metal-oxide-semiconductor transistor and hence limits reductions in transistor threshold voltage and hence chip operating voltage. In contrast to electronic switches, mechanical switches (“relays”) operate by making/breaking physical contact and therefore offer the ideal characteristics of zero off-state leakage current and abrupt transition between on/off states, which provide for zero static power dissipation and (in principle) lower operating voltage, so that they potentially can provide a means for overcoming this crisis. In order to fully realize their promise, however, miniaturized relays must operate with sufficient reliability to be viable for ultra-low-power digital logic applications.

In this work, the reliability of micro-relays designed for digital logic applications is systematically investigated. Contact resistance (Ron) instability is identified as the limiting factor for micro-relay endurance. Due to surface oxidation, Ron of prototype relays with tungsten (W) contacting electrodes increases with the number of operating cycles. This phenomenon is affected by relay operating conditions, including switching frequency and contact force. Larger contact force is found to be beneficial for stable operation, possibly due to breakdown of the insulating oxide layers. An alternative contact electrode material, ruthenium (Ru), is demonstrated to ameliorate the problem of metal surface oxidation; however, friction polymer formation and material transfer become dominant contact reliability issues, which eventually degrade Ron. An inkjet-printed micro-shell encapsulation process is used to provide an isolated ambient environment for the logic relays, and demonstrated to result in improved Ron stability by 100× as compared to devices tested in atmospheric conditions.

In complementary logic circuits, slower switch turn-off than turn-on results in undesirable "crowbar” current, causing transient power dissipation during signal transitions and potential reliability issues. The effects of the contact electrode material mechanical properties, relay design parameters, and relay operating conditions on contact detachment delay (τCD) are experimentally studied and theoretically explained. Specifically, τCD is compared for logic relays with tungsten, ruthenium or nickel contacting electrode materials, and tungsten is found to provide for the smallest τCD.

Over 40 years of scaling dimensions for new and continuing product cycles has introduced new challenges for transistor design. As the end of the technology roadmap for semiconductors approaches, new device structures are being investigated as possible replacements for traditional metal-oxide-semiconductor field effect transistors (MOSFETs). Band-to-band tunneling (BTBT) in semiconductors, often viewed as an adverse effect of short channel lengths in MOSFETs, has been discussed as a promising current injection mechanism to allow for reduced operating voltage for beyond MOSFET technology.

This dissertation discusses the proposal of BTBT for tunneling feld effect transistors (TFETs). Some early work is briefly reviewed to better appreciate the academic research landscape regarding BTBT. Then, experimental observations of a steeply switching enhanced-Schottky-barrier MOSFET are analysed in detail and the steep characteristic is plausibly explained by metal impurity trap states near the source tunneling junction. Next, follow-up experiments to investigate the role of traps in BTBT are reviewed with a likely explanation that traps in close proximity to the tunneling junction can lower the activation energy for BTBT. Finally, a source design study for a planar homojunction germanium-on-insulator TFET finds that a static reverse bias can dramatically alter the optimal doping profile for the source tunneling junction and highlights the importance of tight electrostatic control for improved I_ON/I_OFF in TFETs.

Historically, the steady miniaturization of the conventional (planar bulk) MOSFET by simply scaling the device dimensions with minimal changes to the conventional transistor design and CMOS process flow has been effective to provide for continual improvements in integrated circuit performance and cost per function with every technology node. However, transistor scaling has become increasingly difficult in the sub-100 nm regime. Increased leakage current and variability in transistor performance are the major challenges for continued scaling of bulk-Si CMOS technology.

The benefit of using a spacer gate lithography process to mitigate the effect of gate line edge roughness (LER) is assessed using statistical 3-D device simulations. The simulation results indicate that spacer gate lithography is a scalable technology which can dramatically reduce LER-induced variation in transistor performance.

A tri-gate bulk MOSFET design combining retrograde channel doping with a multi-gate structure is proposed to provide an evolutionary pathway for bulk CMOS scaling. The scalability, design optimization, and the effect of systematic and random variations on transistor performance are investigated. As compared with the classic planar MOSFET design, the tri-gate bulk MOSFET provides for superior electrostatic integrity and reduced variability. As compared with SOI FinFET design, the tri-gate bulk MOSFET design is more scalable and less sensitive to device design parameters. As compared with the bulk FinFET design, the tri-gate bulk MOSFET offers comparable performance and variability. Its low-aspect-ratio channel structure is favorable for ease of manufacturing. Thus, the tri-gate bulk MOSFET is a promising structure for CMOS scaling to the end of the technology roadmap.

The fabrication process flow and the most critical processes for tri-gate bulk MOSFET fabrication are discussed. Initial device results show that tri-gate bulk MOSFET design is beneficial for reduced variability.

CMOS has been the building block for modern digital logic for decades and the performance and energy efficiency of CMOS continues to improve as technology develops, mainly through scaling. However due to the 60 mV/dec limit on MOS transistors, continue to reduce the power supply voltage would result in an increase in off-stage leakage current that would eventually dominate and increase the energy per operation of a transistor. In order to overcome this barrier, mechanical switches are proposed. Mechanical relays has the benefit of no leakage current through the air gap in the off state, which potentially enables further scaling of power supply voltage that can surpass MOS transistors. Several groups have been able to demonstrate mechanical switches with no leakage and abrupt on-off switching characteristics, however both the sizes of switches (~10⁴ μm²) and the operation voltages (> 10 V) are huge, causing the switching energy to be significantly larger than MOS transistors. Scaling efforts are needed to minimize the switching energy of a mechanical switch.

In this thesis, prototype relay devices demonstrated by previous studies are discussed and the key factors that need to be addressed in order to minimize the switching energy are pointed out. The minimum switching energy is found to be limited by the contact adhesive force between contacts; studies on prototype devices with different contact areas shows that van der Waals force between contacts are the main source of adhesion in the prototype mechanical relays. Experiments show that by adding surface coating materials with low Hamaker constant can lower the contact adhesive force. In order to lower the structural stiffness, process development of poly-SiGe is optimized through multiple post-deposition processing techniques for reduced stress gradient of 100 nm thin films, a 10X reduction from the prototype devices. The combined learning from adhesive force work and thin film processing leads to the experiments of fabricating scaled devices of 500X smaller footprint. The results show that scaled relays can potentially operate at low voltages (~2V), but more process optimization needs to be done to demonstrate a fully operational device.

The conventional planar bulk MOSFET is difficult to scale down to sub-20nm gate length, due to the worsening performance variability and short channel effects. Thin body transistors, including Multiple-Gate (FinFET & Tri-Gate FET) and Fully Depleted SOI (FD-SOI) MOSFETs are anticipated to replace the current transistor architecture, and will be used in future CMOS technology nodes. Strained Silicon technology is widely used today to boost planar bulk transistor performance. Thus it's technically important to examine the strain-induced performance enhancement in these thin body transistors, for nanometer scale channel length. A comprehensive study on impact of channel stress on ultra-thin-body FD-SOI MOSFETs is presented. It's found that strain-induced mobility enhancement diminishes with Silicon body thickness scaling below 5nm for electrons, but not for holes. Strain-induced carrier transport enhancement is maintained with gate-length scaling. By applying forward back biasing (FBB) through the ultra-thin Buried Oxide layer, both carrier mobilities and their responses to strain get enhanced. For Multiple-gate FETs, the impact of performance enhancement through various types of stressors (including CESL, SiGe Source/Drain, Strained SOI and Metal Gate Last process) is studied, for different fin crystalline orientations and aspect ratios, to provide guidance for 3-D transistor design optimization.

Complementary-Metal-Oxide-Semiconductor (CMOS) technology scaling has brought about an integrated circuits (IC) revolution over the past 40+ years, due to dramatic increases in IC functionality and performance, concomitant with reductions in cost per function. In the last decade, increasing power density has emerged to be the primary barrier to continued rapid advancement in IC technology, fundamentally due to non-zero transistor off-state leakage. While innovations in materials, transistor structures, and circuit/system architecture have enabled the semiconductor industry to continue to push the boundaries, a fundamental lower limit in energy per operation will eventually be reached. A more ideal switching device with zero off-state leakage becomes necessary.

This dissertation proposes a solution to the CMOS power crisis via mechanical computing. Specifically, robust electro-mechanical relay technologies are developed for digital circuit application. A 4-Terminal (4T) relay design is firstly developed. Key technology features include tungsten contacts for high endurance; low-thermal-budget p+-poly-Si_0.4Ge_0.6 structure for post-CMOS process compatibility; Al₂O₃ as a reliable insulation material; dry release step to mitigate stiction; and folded-flexure design to mitigate the impact of residual stress. Fabricated relays show good conductance (R_ON < 10 kΩ), abrupt switching behavior (sub-threshold swing below 0.1 mV/dec), and virtually zero leakage (I_OFF ~ 10^-14 A). Switching delay in the 100 ns range and endurance exceeding 10⁹ on/off cycles is achieved with excellent device yield (> 95%). With relay design and process optimizations, pull-in voltage below 10 V with less than 1 V hysteresis is achieved. Miniaturization reduces the device footprint to 35μm×50μm, ~10% of the first generation device footprint (120μm×150μm). Relays with multiple source/drain electrodes and multiple gate electrodes are proposed for increased circuit functionality and reduced device count.

Finally, simple relay-based logic circuits are demonstrated to show pathways to relay-based digital integrated circuits. The complementary inverter is the basis for all digital logic circuits and is investigated in depth. Relay-based logic gates are demonstrated using CMOS-like and relay-specific design approaches. Multi-input/multi-output relays are proposed to enable any complex logic function to be implemented compactly with only two relays.

Within every process of electronic device fabrication and subsequent device use, there exists an inherent temperature limitation. This limitation can be part of a particular processing step or a target specification of device operation. To determine the temperature restrictions required by a device and its fabrication, the material system and target application of the resultant device must be assessed, as the thermal budget will vary based on both of these factors. If the temperature limit imposed on a device and its process becomes low enough, measures must be taken to ensure a reduction in thermal load is met without sacrificing the integrity of the constituent materials or the final device behavior. More specifically, these measures result in the development of low temperature materials deposition techniques, devices with reduced power consumption, or low temperature in-line processing techniques. In this dissertation, I will present solutions to circumvent temperature limitations in three areas: transparent flexible electronics, small-scale gas sensors for the Internet of Things (IoT), and back-end-of-line (BEOL) processing steps of state-of-the-art integrated circuits (ICs).

First, in Chapter 2, a novel method of metal oxide material deposition for flexible thin film transistors (TFTs) will be discussed. Materials characterization indicates this material is of high quality suitable for flexible electronics, demonstrated via fabrication of fully transparent all-oxide flexible TFTs. Second, in Chapter 3, a chip-integratable pollutant gas sensor based on silicon transistors is discussed. Transistor-based gas sensing leverages IC manufacturing and enables low temperature operation, allowing for lower power consumption carbon monoxide sensors for air quality monitoring and personal pollution tracking. Lastly, Chapter 4 will present a novel low cost fully-BEOL-compatible nanoscale patterning method based on tilted ion implantation and conventional deep ultraviolet (DUV) lithography. Utilizing silicon-containing spin-on films, patterns on the order of 20 nm are achieved, providing an alternative lithographic method for state-of-the-art transistor fabrication with nanoscale features.