Low Thermal Budget Process Engineering for Flexible Electronics, Sensors, and Nanoscale Patterning
- Rembert, Thomas Ryland
- Advisor(s): King Liu, Tsu-Jae
Within every process of electronic device fabrication and subsequent device use, there exists an inherent temperature limitation. This limitation can be part of a particular processing step or a target specification of device operation. To determine the temperature restrictions required by a device and its fabrication, the material system and target application of the resultant device must be assessed, as the thermal budget will vary based on both of these factors. If the temperature limit imposed on a device and its process becomes low enough, measures must be taken to ensure a reduction in thermal load is met without sacrificing the integrity of the constituent materials or the final device behavior. More specifically, these measures result in the development of low temperature materials deposition techniques, devices with reduced power consumption, or low temperature in-line processing techniques. In this dissertation, I will present solutions to circumvent temperature limitations in three areas: transparent flexible electronics, small-scale gas sensors for the Internet of Things (IoT), and back-end-of-line (BEOL) processing steps of state-of-the-art integrated circuits (ICs).
First, in Chapter 2, a novel method of metal oxide material deposition for flexible thin film transistors (TFTs) will be discussed. Materials characterization indicates this material is of high quality suitable for flexible electronics, demonstrated via fabrication of fully transparent all-oxide flexible TFTs. Second, in Chapter 3, a chip-integratable pollutant gas sensor based on silicon transistors is discussed. Transistor-based gas sensing leverages IC manufacturing and enables low temperature operation, allowing for lower power consumption carbon monoxide sensors for air quality monitoring and personal pollution tracking. Lastly, Chapter 4 will present a novel low cost fully-BEOL-compatible nanoscale patterning method based on tilted ion implantation and conventional deep ultraviolet (DUV) lithography. Utilizing silicon-containing spin-on films, patterns on the order of 20 nm are achieved, providing an alternative lithographic method for state-of-the-art transistor fabrication with nanoscale features.