The output of high-level synthesis typically consists of a netlist of generic RTL components and a state sequencing table. While module generators and logic synthesis tools can be used to map RTL components into standard cells or layout geometries, they cannot provide technology mapping into the data book libraries of functional RTL cells used commonly throughout the industrial design community. In this paper, we introduce an approach to implementing generic RTL components with technology-specific RTL library cells. This approach addresses the criticism of designers who feel that high-level synthesis tools should be used in conjunction with existing RTL data books. We describe how GENUS, a library of generic RTL components, is organized for use in high-level synthesis and how DTAS, a functional synthesis system, is used to map GENUS components into RTL library cells.

By mixing design styles during synthesis of RTL components such as adders, multipliers, and ALUs, it is possible to generate a range of designs from small to fast, where intermediate designs make favorable and possibly desirable tradeoffs between area and delay. Although module generators can be written to reflect design styles that reduce either area or delay, the current approach to generator execution does not examine the effects of mixing different design styles. We have developed an approach to RTL component synthesis that searches the space of design alternatives, and we have implemented this approach with the DTAS Design Language. The significance of our approach is that it allows DTAS to generate designs use a combination of design styles and to compare the effects of mixing styles. In this paper, we outline the operation of DTAS and describe how DTAS expands and constrains the design space. We present results from applying DTAS to large RTL components using an MCNC benchmark library. We also present results of integrating DTAS with the MISII logic optimizer.

The goal of design synthesis is the generation of high-quality material designs from abstract specifications. Recent efforts in VLSI design synthesis (logic synthesis) have shown how heuristic techniques can generate human-quality hardware designs in a fraction of manual design time. Despite successes, the state of the art in logic synthesis is limited in terms of range and quality. Existing logic synthesis tools are largely restricted to designing combinational circuits described by Boolean equations. Such circuits compose only about 20 percent of a high-level design; the other 80 percent consists of complex components described in terms of their functionality, such as arithmetic and logic units, counters, and processors. Existing tools are also restricted to implementing designs with a small set of widely available physical cells, such as one- and two-level Boolean gates. While this restriction makes a synthesis tool independent of a particular component library, it also keeps the tool from using complex but nonstandard library components that might otherwise improve design quality.

To increase the capabilities and quality of synthesis tools, we propose to develop a new knowledge-intensive model of design synthesis that we call the derivational-process model. This model uses knowledge of design styles to decompose component specifications and generate designs that are appropriate to constraints. To keep this model robust to technology changes, we further propose to develop an adjunct learning component called the model of technology adaptation. This model uses knowledge of fundamental principles of design to acquire design rules that take advantage of complex library components or that reflect new design styles. The combination of these two models we refer to as adaptive design synthesis. This work contributes to recent work in Logic Synthesis, Knowledge-Based Design, and Machine Learning.