BioCoder is a domain-specific language by which chemists and biologists can express experimental protocols in a manner that is unambiguous and clearly repeatable. This paper presents a software toolchain that converts a protocol specified in a restricted subset of BioCoder to a technology-specific description of the protocol, targeting flow-based microfluidic large-scale integration (mLSI) chips. The technology-specific description can then be used to either: (1) execute the protocol on a capable chip; or (2) to derive the architecture of a new mLSI chip that can execute the protocol. © 2013 IEEE.

This paper introduces a field-programmable pin-constrained digital microfluidic biochip (FPPC-DMFB), which offers general-purpose assay execution at a lower cost than general-purpose direct addressing DMFBs and highly optimized application-specific pin-constrained DMFBs. One of the key cost drivers for DMFBs is the number of printed circuit board (PCB) layers, onto which the device is mounted. We demonstrate a scalable single-layer PCB wiring scheme for several FPPC-DMFB variations, for PCB technology with orthogonal routing capacity of at least three; for PCB technology with orthogonal capacity of two, more PCB layers are required, but the FPPC-DMFB retains its cost advantage. These results offer new insights on the relationship between PCB layer count, pin count, and cost. Additionally, to reduce the execution time of assays on the FPPC-DMFB, we present efficient algorithms for droplet routing, with and without contamination removal via wash droplets.

Virtual topologies simply the process of compiling assays to execute on digital microfluidic biochips (DMFBs). This paper evaluates the performance and cost of a virtual topology inspired by networks-on-chip (NoCs). The throughput of several deadlock-free droplet routing protocols is compared on synthetic traffic patterns that are widely used to evaluate semiconductor NoCs. The cost is the number of control pins required for actuation and the number of PCB layers required to route the chip; by eliminating unused pins, the virtual topology is cheaper than a direct-addressing DMFB, especially as chip size increases.

This paper describes an integrated design, verification, and simulation environment for programmable microfluidic devices called laboratories-on-chip (LoCs). Today's LoCs are architected and laid out by hand, which is time-consuming, tedious, and error-prone. To increase designer productivity, this paper introduces a Microfluidic Hardware Design Language (MHDL) for LoC specification, along with software tools to assist LoC designers verify the correctness of their specifications and estimate their performance. © 2013 IEEE.

This paper introduces a multi-terminal escape routing algorithm for the design of Printed Circuit Boards (PCBs) that control Digital Microfluidic Biochips (DMFBs). The new algorithm is based on the principle of negotiated congestion, which has been applied in the past to problems including FPGA routing and PCB escape routing for single-terminal nets. PCBs designed for Pin-constrained DMFBs, in which one control pin may drive multiple electrodes, require multi-terminal escape routing solutions. Experimental results indicate that negotiated congestion is more effective for multi-terminal escape routing than existing techniques, which are based on maze routing coupled with rip-up and re-route, yielding an overall reduction in the number of PCB layers in most the test cases that were tried.

This paper introduces a multiterminal escape routing algorithm for the design of printed circuit boards (PCBs) that control digital microfluidic biochips (DMFBs). The new algorithm extends a negotiated congestion-based single-terminal escape router that has been shown to be superior to previous methods. It relaxes the pin assignment to allow pin groups to be broken up when doing so can reduce the number of PCB layers. Experimental results indicate that the improved method can reduce both the number of PCB layers and average wirelength compared to existing DMFB escape routers.

Microfluidic large-scale integration (mLSI) chips comprise hundreds or thousands of microvalves integrated into a chemically inert elastomeric substrate. The design of these chips is time-consuming, error-prone, and presently performed by hand. To enhance design automation, a routability-oriented placement algorithm based on simulated annealing is introduced. This paper investigates relevant issues including: (1) grid representation; (2) perturbation operations; (3) objective function; (4) uniform vs. heterogeneous component sizes; (5) spacing rules and their effect on routability; and (6) random vs. directed initial placement. Our results show how the above issues affect both the pre-routing estimate on the routability of the chips, the number of flow channel intersections (each of which requires the insertion of several microvalves), and total channel distance as reported by our router.

A software toolchain for physical design and layout for the flow layer of microfluidic laboratories on a chip ( LoCs) based on integrated microvalve technology is reported. LoCs based on monolithic membrane valves are built using two glass plates that sandwich a thin layer of polydimethylsiloxane (PDMS), a flexible and inert organic polymer. Etched channels in the two glass plates, respectively, provide distinct layers for fluid and pneumatic control. The biochemical reaction executes on the flow layer, while the control layer delivers pressure to each microvalve to control fluids in the flow layer. The planar layout for the fluid flow layer is converted to a scalable vector graphic (SVG) file, which can be used to create a mask that produces patterns for etched channels in one of the two glass layers. If a legal placement and routing solution is not found at N hops, then we try again at N=2 hops, etc. This ensures that a legal placement and routing solution is found for each perimeter component after O(log N) routing attempts. It is clear from a straightforward visual inspection that numerous local perturbations to the component layout could reduce chip area and/or fluid routing channel length.

In recent years, significant interest has emerged in the problem of fully automating the design of microfluidic very large scale integration (mVLSI) chips, a popular class of Lab-on-a-Chip (LoC) devices that can automatically execute a wide variety of biological assays. To date, this work has been carried out with little to no input from LoC designers. We conducted interviews with approximately 100 LoC designers, biologists, and chemists from academia and industry; uniformly, they expressed frustration with existing design solutions, primarily commercially available software such as AutoCAD and Solidworks; however, they expressed limited interest and considerable skepticism about the potential for 'push-button' end-to-end automation. In response, we have developed a semi-automated mVLSI drawing tool that is designed specifically to address the pain points elucidated by our interviewees. We have used this tool to rapidly reproduce several previously published LoC architectures and generate fabrication ready specifications.