In this report we briefly describe a set of designs that can serve as examples for High Level Synthesis (HLS) systems. The designs vary in complexity from simple behavioral finite state machines to more complex designs such as microprocessors and floating point units. Most of the designs are described in the VHDL language at the behavioral level. The report describes two categories of designs. The first category contains designs that have documentation on the specifications of the designs along with the strategy used to test the individual design models. The second category contains examples used in many HLS papers, but lack comprehensive decumentation and/or test vectors.

Behaviors describing image processing algorithms manipulate arrayed variables that are typically mapped to memories. These algorithms form the heart of portable communication and multimedia applications that demand low power, hence power reduction of memory systems is a critical task.

In this report we present low power techniques for mapping arrays in the behavior to physical memory, specifically for memory intensive behaviors that exhibit regularity in their memory access patterns. Our approach exploits this regularity in memory accesses by reducing the number of transitions on the memory address bus.

We present different strategies for mapping arrays in behaviors to physical memory and study their impact on power dissipation. We describe an algorithm for selecting a memory mapping strategy to achieve low power. We conducted experiments on several image processing benchmarks and observed power savings of upto 56 % through reduced transition activity on the memory address bus.

Code generation for embedded processors opens up the possibility for several performance optimization techniques that have been ignored by traditional compilers that typically do not exploit architectural features of embedded processors such as paramaterized caches. In this report, we present techniques that take into account the parameters of the data caches, for organizing variables declared in embedded code into memory, with the objective of improving data cache performance. We present techniques for clustering variables to minimize compulsory cache misses, and for solving the memory assignment problem to minimize conflict cahce misses. Our experiments with benchmark code kernels from DSP and other domains on the CW4001 embedded processor from LSI Logic indicate significant improvements in data cache performance (average improvement of 42% in hit ratios) by the application of our memory organization technique.

Efficient utilization of on-chip memory space is extremely important in modern embedded system applications based on microprocessor cores. In addition to a data cache that interfaces with slower off-chip memory, a fast on-chip SRAM, called Scratch-Pad memory, is often used in several applications. We present a technique for efficiently exploiting memory by partitioning the application's scalar and arrayed variables into off-chip DRAM and on-chip Scratch-Pad SRAM, with the goal of minimizing the total execution time of embedded applications. Our experiments on code kernels from typical applications show that our technique results in significant performance improvements.