An innovative approach for creating miniature Inertial Measurement Units (IMU's) has been developed using folded MEMS fabrication. This enables a path toward a high-performance IMU with a chip-scale footprint of <1 cm^2. The explored method of manufacturing chip-scale IMUs utilizes folded MEMS structures rather than chip stacking or single-die implementations. Inertial measurement units have previously been developed to detect translational and rotational motion, and miniaturization of such technology is desired for many applications. A fabrication process is developed in this work for creating chip-level IMU's utilizing a 3-D SOI backbone which is suitable for high-performance single-axis sensors with an overall package volume of 1 cm^3 or less.

Inertial sensor test structures are designed and implemented on prototype IMU structures. Conventional packaging methods are used such as wirebonding and flip-chip die attachment to connect the sensor bond pads to the overall package. Results indicate that the scale factors are found to be 0.43 mV/°s for the gyroscopes and 3.7 Hz/g for the accelerometers. Methods for providing reinforcement of the folded MEMS devices are explored including epoxy bonding, eutectic soldering, and silicon welding. Folded structures reinforced with silicon welding resulted in survival of up to 260 g of acceleration and experienced its first modes of resonance above 10 kHz.

Performance estimation of the capabilities of the folded MEMS IMU devices is simulated with a mathematical error model. A coordinate transformation is defined to translate the inertial sensor vector axes to navigational frame coordinates. Transformations from the IMU body frame to the navigational frame are created for pyramidal and cubic folded IMU structures. The resulting calculated CEP rate values indicate that the device is capable of moderate navigational performance compared to current technology. This type of IMU shows an overall performance advantage compared to existing chip-scale IMU devices, and is capable of producing a moderate-performance chip-scale device that exceeds the currently available technology.