CMOS scaling has outpaced manufacturing technology advancements, and consequently process variability continues to increase. Manufacturing non-idealities induce variations in lateral dimensions and topography, stress variations, and material variations. These are manifested as circuit delay and power variations, and consequently low parametric yield, which is the percentage of chips that, though functional, fail to meet delay and power specifications. Design for manufacturing (DFM) refers to measures taken during design to enhance yield. Traditional DFM techniques are essentially geometric operations with limited electrical interactions or awareness. These include resolution enhancement techniques to improve fidelity of optical lithography, design rule checks to restrict the use of layout patterns not amenable to manufacturing, and guardbanding to keep margins for process variability in design. As the extent and complexity of process variations increases, and suboptimality due to conservative design threatens to offset the benefits of scaling, these traditional DFM techniques, while still crucial, are no longer adequate. DFM techniques to improve parametric yield can be classified according to their approach. A considerable fraction of variability is systematic in nature and can be predicted using layout and process knowledge. Examples of such variations are pitch-dependent lithography variations and layout-dependent stress effects. These variations can be predicted and compensated for in physical design to improve yield. A second class of DFM techniques enhances design robustness to process variations. Examples include gate length biasing and redundant link insertion in clock trees, which respectively reduce leakage and clock skew variations even when the gate length variability remains the same. A third class of parametric yield-directed DFM techniques reduces process variations themselves, and includes dummy fill insertion and the increased use of layout pattern regularity. In this thesis we propose novel DFM techniques that explicitly target parametric yield. We present three techniques for analysis and optimization of circuit leakage and delay that are knowledgeable of systematic lithography variations due to pitch, defocus, and lens aberration. Stress variations, due to width of shallow trench isolation (STI) wells, can lead to considerable delay variations. We propose timing analysis and optimization methodologies to account for STI width- dependent stress, which is highly systematic in nature. Variations in gate length arising from a variety of process variations are a major cause of leakage variability, an important problem being faced by the designers today. We propose gate length biasing, which leverages the threshold voltage roll-off to significantly reduce leakage and its variability. The technique is non- obtrusive to existing flows, easy to adopt, and inexpensive to manufacture. We also present our contributions to front-end of the line (FEOL) and back-end of the line (BEOL) fill. Our FEOL insertion methodology considerably improves topography after chemical mechanical polishing for STI and may avoid the need for reverse- etchback process steps. In BEOL fill insertion, a primary concern is the capacitive impact of inserted fill and the corresponding increase of delay and crosstalk. We describe a systematic study of the capacitive impact of inserted fill, and develop guidelines that reduce capacitive impact without sacrificing metal density

In this talk we highlight how Zeek can play a crucial role in enabling various tenets of Zero-Trust. We start with looking at fundamental design goals of Zeek itself from the time when Zero-trust was not even a buzzword. We further discuss Zero Trust security models – specifically the Networking Piller – and how Zeek can facilitate Zero Trust postures of visibility, automation and analytics. At the end of this talk we focus on Zeek’s challenges in optimal zero trust implementation and discuss possible solutions.

We provide a detailed study of the application of wireless sensor networks to a real-world building management system. A set of design requirements was discussed for the development of a sensor network architecture for an HVAC control system. We propose a system architecture that can be easily integrated into any existing building control system. We implemented a testbed to evaluate control strategies using ad hoc wireless sensors. The testbed was designed within the controlled environment chamber in the College of Environmental Design and UC Berkeley. Preliminary results from control strategies have allowed us to determine the effectiveness of the sensor network. The design of the system was suited for the kind of control applications that are indicative of the field. We discussed the lessons learned from our tests and propose future experiments with multiple ad hoc sensors to fully investigate the value added benefit of integrating this technology into the legacy architecture.

Hands-on Zeek Scripting training, Aashish Sharma will walk attendees through the fundamentals of Zeek Scripting along with some practical exercises. This training will cover scripting basics, and will then advance through various Zeek script frameworks. In the training, we will cover how to work with Zeek events and datatypes, how to create custom datatypes, how to create custom log-files and notices, how to use probabilistic datastructures, how to load data into Zeek. We also will talk about some clusterization techniques. The training will end by walking attendees through the process of developing a new heuristic and wrapping it into a package. This will be a hands-on training. There will be an introduction for each topic, followed by hands-on exercises.

Most research on allyship in the racial domain focuses on White allies while overlooking allies from other racial/ethnic minority groups. White allies and racial/ethnic minority allies may have different motives for supporting the targeted group. The current study assessed the perceived motivations of White and racial/ethnic minority allies from the perspective of the targeted group. The study was conducted between subjects, in which half of the participants read a vignette on an example of White allyship during a BLM protest, while the other half read a vignette on an example of Latinx allyship during a BLM protest. We found that Black Americans perceived Latinx allyship during a Black Lives Matter (BLM) protest to be significantly more outgroup motivated, morally motivated, internally motivated, ingroup motivated, less personally motivated, and less externally motivated than White allyship.

Bro Exchange 2012, National Center for Atmospheric Research (NCAR), Boulder, Co, Aug 7-8, 2012

Challenges and Strategies for Network monitoring in an Open Research Network