With the number of cores on a chip continuing to increase, we are moving towards an era where many-core platforms will soon be ubiquitous.

Efficient use of tens to hundreds of cores on a chip and their memory resources comes with unique challenges.

Some of these major challenges include:

1) Data Coherency -- the need for coherency protocol and its induced overhead poses a major obstacle for scalability of many-core platforms.

2) Memory requirement variation -- concurrently running applications on a many-core platform have variable and different memory requirements, not only across different applications, but also within a single application;

in this dynamic scenario, static analysis may not suffice to capture dynamic behaviors.

3) Scalability -- inefficiency of a central management makes distributed management a necessity for many-core platforms.

To address all these issues, this dissertation proposes a comprehensive approach to manage available memory resources in many-core platforms equipped with Software Programmable Memories (SPMs). The main contributions of this dissertation are: 1) We introduce SPMPool: a scalable platform for sharing Software Programmable Memories. The SPMPool approach exploits underutilized memory resources by dynamically sharing SPM resources between applications running on different cores and adapts to the overall memory requirements of multiple applications that are concurrently executing on the many-core platform. 2) We propose different central and distributed management schemes for SPMPool and study the efficiency of auction-based mechanisms in solving the memory mapping problem. We also introduce a distributed auction-based scheme to manage the memory resources of platforms without central coordination. 3) We introduce offline and online memory phase detection methods in order to increase the adaptivity of memory management to the temporal changes in memory requirements of a single application. We also use memory phasic information to relax the need for static analysis of applications.

We implemented a Java and Python based simulator for many-core platforms to investigate the efficacy of the proposed methods in this dissertation.

The runtime memory management schemes proposed here enable better performance, power, and scalability for many-core systems.