Microarchitectural simulation of multithreaded architectures with shared resources, such as simultaneous multithreading (SMT) cores and multi-core processors with shared caches, is time-consuming and the results of simulation may be difficult to interpret. It is time- consuming because modern benchmarks run for hundreds of billions (or even trillions) of instructions, and accurate multi-core and SMT simulation requires higher-detail models than single-threaded simulation. The statistics collected when two programs execute together can be difficult to interpret because the programs both exhibit independent phase behavior and affect each other's execution. Starting one program slightly later than during the original execution will change the phases that execute together and thus change the effects that the programs have on each other. Accurate sampled simulation requires accurate sample collection. We evaluate techniques to improve sampling accuracy and performance, both for single -threaded and multithreaded simulation. These techniques include warming the CPU with detailed execution, storing cache state and techniques to minimize the size of checkpoints. Previous work showed that single-program performance can be accurately estimated by dividing execution into phases and only simulating representative samples from each phase. We demonstrate that the juxtaposition of phases (̀co-phase') from a pair of programs has similar behavior to a single-threaded phase. Furthermore, simulation of all possible co-phases allows analysis of all distinct SMT behaviors and this comprehensive knowledge of program interactions can be combined with information about the sequence of phases executed by each program to reconstruct the combined execution of the programs from any given starting point. Given the short samples, the set of executions from all possible starting offsets can be sampled in minutes, determining the average performance of the programs. This removes the problem of interpreting the results of small numbers of experiments. Finally, we propose three techniques for using the co-phase techniques to summarize the behavior of all possible interactions within a suite of benchmarks. We reduce the scale of this problem using Principle Components Analysis, allowing our techniques to scale to large numbers of benchmarks an concentrate simulation on the most significant behaviors

Simultaneous Multithreading (SMT) architectures are appearing in commercial processors, yet there is still relatively little support for sampling or determining where to simulate to achieve representative simulation results. The challenge in creating a sampling approach to SMT is determining how far to fast-forward each individual thread between samples. Determining how far to accurately fast-forward each individual thread will vary as the threads execute through different phases of execution, and between different architecture configurations. In this paper, we examine using individual program phase information to guide simulation for Simultaneous Multithreading. This is accomplished through creating what we call a Co-Phase Matrix. The co-phase matrix represents the performance and throughput of the potential combination of the phase behavior found in multiple programs when run together. The co-phase matrix is populated by collecting samples of the program's phase combinations, and is used to to guide how far to fast-forward between samples. We show for a handful of SPEC program combinations that using the co-phase matrix provides an average error rates of 2.2% while replacing most detailed simulation with fast-forwarding.

Pre-2018 CSE ID: CS2003-0771

Modern architecture research relies heavily on detailed pipeline simulation. Simulating the full execution of an industry standard benchmark can take weeks to months. Statistical sampling and techniques like SimPoint that pick small sets of execution samples have been shown to provide accurate results while significantly reducing simulation time. The inefficiencies in sampling are (a) needing the correct memory image to execute the sample, and (b) needing to having warm architecture state when simulating the sample. In this paper we examine efficient Sampling Startup techniques for representing the correct memory image during simulation, and for dealing with warmup. Representing the correct memory image ensures the memory values consumed during the sample's simulation are correct. Warmup techniques focus on reducing error due to the architecture state not being fully representative of the complete execution that proceeds the sample to be simulated. This paper presents several Sampling Startup techniques and compares them against previously proposed techniques for both uniprocessor and simultaneous multithreading architecture simulation.

Pre-2018 CSE ID: CS2004-0803

Transactions have emerged as a promising way to exploit thread-level parallelism in the presence of shared data. Preventing data-races between threads traditionally implies lock-based synchronization. This comes at the risk of deadlock due to programmer error, and overly-conservative locking will limit the performance potential of parallel execution. Transactions circumvent these limitations by detecting and serializing data dependencies between threads at runtime without the need for locks. Hardware supported transactional memory builds on top of the cache coherence mechanism of shared memory multi-processors to detect data dependence conflicts between concurrent transactions. Recent proposals address the need to support the virtualization of transactions when the finite capacity of the cache is exceeded. These techniques have either a fast commit or abort, but not both. Similarly they support either fast conflict detection but are not able to handle swapped processes, or slow but complete. In this paper we examine page-based transactional memory to provide virtual transactions. We combine transaction bookkeeping with page address translation for fast conflict detection with fast access of overflowed transactional data. Our approach provides fast virtual transaction commit and abort, and conflict detection. We provide quantitative measurement of performance, whereas most examinations of virtualized transaction techniques provide only theoretical analysis of performance.

Pre-2018 CSE ID: CS2005-0848