With the continuous demands on integrating more functions and devices on a single chip, the technology has been evolving along the scaling path for decades. The transistor feature size has been scaled down from μm order toward 7nm, 5nm, and even below. Conventional MOSFET / FinFET devices are approaching physical limitations. It is extremely difficult to integrate more devices solely by further transistor scaling. Besides scaling, 3D integration technologies offer attractive features. By stacking devices, it increases device density and reduces wire length, which implies better PPA (performance, power consumption, and area). However, the increased power density and the extra overhead of inter-tier connections are significant concerns for deploying 3D integration technologies. For sustaining future technology growth, it is expected that fundamental changes of device structure are required.

Vertical Slit Field Effect Transistor (VeSFET) is a novel transistor with unique structure and characteristics. It is two-side accessible and low power consuming, which is 3D integration friendly. This dissertation investigates VeSFET technology and proposes unique and powerful applications, which are not feasible using MOSFET technologies. The scope of our studies includes SRAM, monolithic 3D physical design assessment, 3D FPGA, fast and hardware predictable ASIC design methodology, high performance reconfigurable architecture with dynamic reconfigurable accelerators, and hardware security.

In this dissertation, SRAM performance assessment shows that VeSFET SRAM is speed competitive to CMOS SRAM and consumes much less power. The monolithic 3D physical design assessment compares MOSFET and VeSFET monolithic 3D integrated circuits. In particular, the IR-drop on power delivery network (PDN) and clock distribution network (CDN) characteristics are assessed. Due to VeSFET’s lower power consumption, 3D VeSFET ICs have lower IR-Drop and CDN power consumption. A fast, fully verifiable, and hardware predictable ASIC design methodology using VeSFET 3D FPGA is presented. The performance comparison of VeSFET 2D and 3D FPGA shows that the 3D FPGA is faster, smaller, and consumes less power. A high performance reconfigurable architecture is proposed using VeSFET fast reconfigurable 3D FPGA-based accelerators with novel bitstream replacement method. The system level performance evaluation shows significant improvement over the system with no accelerator or with conventional FPGA-based accelerator. Toward trustworthy hardware designs, a secure split-fabrication method using VeSFET is proposed for addressing hardware security concerns, such as piracy prevention, hardware Trojan prevention and detection. Any Trojan insertion or design tampering can be easily detected.