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Open Access Publications from the University of California

The Effect of Offcut Angle on Electrical Conductivity of Direct Wafer-Bonded n-GaAs/n-GaAs Structures for Wafer-Bonded Tandem Solar Cells

  • Author(s): Yeung, King Wah Sunny
  • Advisor(s): Goorsky, Mark S
  • et al.

III-V compound semiconductors possess advantageous materials properties, such as direct bandgap and high carrier mobility, which make them attractive in optoelectronic, fiber optical communications and high-speed digital circuit applications. Integration of III-V heterostructures using direct wafer bonding has the added benefit of avoiding constraints in lattice parameter mismatch compared to epitaxially grown devices. As a result, wafer bonding is significant in its ability to integrate mismatched materials and circumvent the issues of inferior device performance due to a high density of threading dislocations.

In the solar industry, off-axis substrates are commonly used in the growth of III-V epitaxial layers to avoid the formation of antiphase boundaries, which act as deep level non-radiative recombination centers. Previously published studies from our research group showed that an additional sulfur-based passivation technique can reduce the density of surface charge states and improve the conductivity across the interface. However, a research topic that has not been investigated is the effect that miscut substrates have on the performance of direct-bonded III-V devices. In this study, the effect of the wafer offcut angle on the electrical conductivity of III-V solar cell devices is investigated using n-GaAs/n-GaAs wafer-bonded structures.

GaAs (001) wafers misoriented towards <111>A are chosen and compared to nominal on-axis substrates. Prior to bonding, the surfaces are treated with either an oxide etch or additional 5-min treatment in aqueous (NH4)2S. Off-axis wafers are positioned face-to-face with a non-zero relative surface misorientation between the tilted (001) planes and low force bonding is initiated at room temperature. The highest degree of misorientation in this study is produced using 6° off-axis wafers and can be represented as a grain boundary with a twin defect at the (1 1 13) plane and a tilt angle of 12° about the common [110] direction. The samples are annealed at 400 °C for two hours to strengthen the bond. It is observed that the electrical conductivity improves considerably with a short rapid thermal processing (RTP) at 600 °C for 2 mins. However, the degree of miscut has a detrimental effect, as both the oxide-etched and sulfur-treated samples exhibit increasingly non-ohmic behavior with greater relative misorientations. A theoretical model that describes the electron tunneling across a grain boundary between semiconductor bicrystals is used to represent the bonded interface and estimate the barrier conduction height. Fitting the zero-bias conductance data over a range of temperatures reveals an increased barrier height for greater offcut angles, with 4° and 6° miscut sulfur-passivated wafers producing a 0.4 eV increase. When compared to on-axis structures, the interface resistance at room temperature increases from 0.01 ohm·cm2 to 3.4 ohm·cm2.

High resolution transmission electron microscopy (HRTEM) and scanning transmission electron microscopy (STEM) are used to compare the interface morphology across the range of relative misorientations after the 600 °C RTP. The ratio of well-bonded crystalline regions to amorphous oxide inclusions is consistent across all bonded samples, indicating that the degree of misorientation does not affect the level of interface recrystallization. It is also observed that regions adjacent to the interface undergo a process of atomic redistribution and recrystallize into the same lattice arrangement as the bulk semiconductor.

The effect of relative surface misorientation on conductivity is further investigated by fabricating zero-degree relative (001) misoriented bonded samples using 6° miscut substrates and subjecting to the same thermal and sulfur passivation treatment. This can be described as a grain boundary at the (1 1 13) plane without any twin defects about the [110] direction. Current-voltage (I-V) characteristics are comparable to nominal on-axis specimen with the interface resistance measured as 0.02 ohm·cm2. It is concluded that the degree of relative misorientation of (001) planes across the bonded interface has a significant impact on the electrical properties, as illustrated by the two orders of magnitude difference in conductance.

Non-ohmic behavior has previously been discovered in direct-bonded n-type GaAs/GaAs structures. In order to pinpoint the source of this inferior conductance, several lines are physically cut into the surface with a diamond scribe to electrically isolate a portion of the metal contacts. I-V measurements are taken at various test points to compare the resistance across the different interfaces. The measured resistance across the metal-metal and metal-semiconductor-metal regions is found to be 0.8 ohms. However, the inclusion of the bonded interface results in a significant increase in resistance to 770 ohms at zero-bias conditions. The non-ohmic behavior is confirmed to be solely attributed to the bonded interface.

These results demonstrate the potential usefulness of using off-axis substrates in the fabrication of direct wafer-bonded III-V heterostructures. More importantly, the primary effect on conductivity does not originate from the miscut substrates themselves. Instead, the out-of-plane relative misorientation of the tilted (001) planes is the critical parameter that needs to be controlled within a manufacturing environment in order to achieve acceptable electrical performance in multijunction solar applications.

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