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Open Access Publications from the University of California

RELIABILITY STUDIES OF Pb-FREE SOLDER JOINTS DOWN TO 1 μm IN DIAMETER

  • Author(s): Liu, Yingxia
  • Advisor(s): Tu, King-Ning
  • et al.
Abstract

In 3D IC, μ-bumps and through silicon vias (TSVs) have been developed to achieve the vertical stacking of Si chips. Similar to the downward scaling of transistors in semiconductor industry, the development in advanced packaging also leads to the scaling down of interconnect structures. Compared to flip chip solder joints having a diameter about 100 μm, the diameter of μ-bumps is reduced 10 times and the total volume is reduced 1000 times. This size reduction of solder joints will lead to many reliability concerns.

In this thesis, the finding that intermetallic compound (IMC) growth rate between solder and Cu under bump metallization increases in small μ-bumps will be analyzed and discussed. The kinetic model for small size Cu-Sn interfacial reaction has been investigated by making different size of Sn pillars on Cu substrate with the use of focused ion beam (FIB), down to 1 μm. With the shrinking size of pillars, surface diffusion becomes dominant and can no longer be neglected in the Cu-Sn interfacial reaction. A simple kinetic model of surface diffusion controlled intermetallic compound growth of Cu6Sn5 is proposed for pillars with diameter below 5 μm by combining surface diffusion and interstitial diffusion. Also, the reliability concern of electroless nickel immersion gold (ENIG) surface finishing on IMC formation when the size of solder is reduced from flip chip solder joints to μ-bumps has been studied. Since the volume of solder shrinks 1000 times in μ-bumps, a thin layer of ENIG will transform almost the entire solder joint into (Au,Ni)Sn4 intermetallic compound. The fracture reliability concern of this brittle phase in μ-bumps will be discussed.

In addition to size shrinking of solder joints, the diameter of Cu lines is also reduced. In 3D IC packaging, there is a layer of Cu used to fan out electric current from flip chip solder joints to TSVs and μ-bumps, and this layer is known as redistribution layer (RDL). In electrimgration test, the weakest link in this whole packaging system is found to be located in the RDL. This is because of the design of RDL, which is composed of very thin Cu due damascene lines and has quite compact structure. Thermal dissipation becomes a problem in this design of RDL. Joule heating will be accumulated and resulting in the increase of temperature, which in turn increase the rate of electromigration depletion of atoms in Cu lines and making the lines thinner and thinner. This synergistic effect of Joule heating and EM on burn-out is a new failure mode of reliability.

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