UCLA

In today's System–on–Chip (SoC) design, both analog and digital circuits play important role. Digital circuits are fully used to build memory and signal processing blocks. With technology scaling, speed of digital circuits has been boosted a lot in deep submicron technologies. Being the interface between real world and digital block, Analog–to–Digital Converter (ADC) is now very critical. Since high speed and high precision is required, ADC has now become a bottleneck in SoC design. Especially when integrated with digital circuits, ADC has to maintain its performance in noisy environment. Therefore, effort is deserved to develop high resolution, low power ADC designs. In this thesis, an 11–bit Pipelined ADC with Op Amp sharing technique is presented. The post–layout simulation shows an SNDR of 59.46dB and SFDR of 69.00dB. Current consumption is around 11mA from 2.5V power supply.