Skip to main content
Open Access Publications from the University of California

High-level timing and power analysis of embedded systems


Timing and power are two metrics that have become increasingly important to system level designers especially with the advent of the system-on-a-chip era. This dissertation combines the analyses of timing and power for system level designs and enables complex timing-power tradeoffs at the. system level itself. It allows system designers to identify subsystems that are timing critical and power critical.

Timing plays an important role in the design of embedded real-time systems. Unfortunately, the process of designing a temporally correct system is a difficult one. The current practice is based on trial and error, guided by engineering experience and therefore is rather ad-hoc. Moreover, the emphasis is usually on designing a functionally correct system first, leaving the temporal correctness to be checked after the system's components are integrated. This usually results in expensive redesign iterations in order to satisfy temporal constraints. In this dissertation, we extend the generalized task graph model proposed for timing models at the system level to include a timing model of communication between nodes (tasks) of the task graph model. We also extend the timing analysis tool, RADHA-RATAN, to identify timing critical subsystems and generate a process timing model for the behavior of the system. This allows designers to simulate the timng behavior of the system with a minimal description of the system's functionality.

Most of the previous work on system level power management are based on experimental observations and heuristics. In this dissertation, we propose techniques that enable the designer to identify power critical subsystems and develop effective power management strategies for them. These strategies are based on shutting down the system after a specific period of time. This dissertation shows that power management techniques for real-time embedded systems can be modeled as on-line problems and examines their efficiency using a formal technique called competitive analysis. We classify algorithms for power management as either adaptive or non-adaptive and analyze their effects on system latency and resources needed to implement them. The results of this dissertation can be used to design effective power management strategies for embedded systems that trade-off system latency, resources and power dissipation.

Main Content
For improved accessibility of PDF content, download the file to your device.
Current View