UC Santa Cruz

Non-volatile memory (NVM) technology has revolutionized memory systems with its non-volatility and near-zero standby power consumption, making it a promising alternative to traditional DRAMs. However, NVMs also face significant challenges, particularly limited write endurance and high energy consumption, which impede their widespread adoption. This thesis contributes to the integration of NVM technologies into the memory hierarchy, addressing these challenges with software-level solutions, including AI-based techniques and data structure-based methods. These approaches enhance energy efficiency and write endurance, improving the practicality and longevity of NVM devices. This thesis is organized into four main parts:

In the first part, we conduct a comprehensive evaluation of real-world NVM devices, such as Optane memory, to explore the effects of memory awareness on performance, energy consumption, and lifetime. Our experiments reveal that memory-aware strategies significantly increase device lifetime, decrease power consumption, and improve system latency. This chapter underscores the importance of integrating recent advances from the NVM storage community into existing and future data management systems.

In the second part, we propose Predict and Write (PNW), a K/V-store that uses a clustering-based machine learning approach to extend the lifetime of NVMs. PNW reduces the number of bit flips for PUT/UPDATE operations by determining the optimal memory location for updated values. By leveraging the indirection level of K/V-stores, PNW organizes NVM addresses in a dynamic address pool clustered by data value similarity. Our results demonstrate that PNW can reduce total bit flips by up to 85% and cache lines by 56% compared to the state of the art.

In the third part, we introduce E2-NVM, a software-level memory-aware storage layer designed to improve the Energy efficiency and write Endurance (E2) of NVMs. E2-NVM employs a Variational Autoencoder (VAE) based design to judiciously direct write operations to memory segments that minimize bit flips. This solution, which can be combined with existing indexing and hardware-based methods, demonstrates a reduction in energy consumption by up to 56% in real-world evaluations on an Optane memory device.

The final part of this thesis presents a software-level data storage layer solution that uses a indexing data structure to improve the energy consumption and write endurance of NVMs. In this work, we presented the case for memory-awareness and showed that by judiciously selecting memory locations for new writes and updates we can reduce bit flipping and consequently improve the energy efficiency and write endurance of NVM devices. We took this concept and built Hamming Tree, with which existing data stores can be augmented, to make them memory-aware. Hamming Tree tackles the challenges associated with mapping free memory locations based on the hamming distance of their content. Our evaluations on an Intel Optane memory device show that Hamming Tree can achieve up to a 67.8% improvement in energy efficiency.

Overall, the methods proposed in this thesis are software-level solutions aimed at improving the performance of NVMs. PNW is the simplest, suitable for systems with fixed memory segment sizes and basic hardware resources, though advanced components can enhance its performance. E2-NVM is more advanced, handling large, variable- sized memory segments and requiring GPUs for maximum efficiency. Hamming Tree, implemented as an indexing data structure, is fast but sensitive to the number of indexed items. This thesis presents a comprehensive framework for enhancing NVM efficiency and longevity, addressing critical challenges like energy consumption and write endurance.