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Open Access Publications from the University of California

Area-selective Atomic Layer Deposition of Silicide and Oxides Using Inherent Substrate Dependent Processes

  • Author(s): Choi, Jong Youn
  • Advisor(s): Kummel, Andrew C
  • et al.
Abstract

For the last three decades, the semiconductor industry continued to grow in all aspects such as the device performance, power efficiency, data process speed, manufacturing yield and costs. One of the most important factors that made this big stride possible was a scaling of metal-oxide-semiconductor field effect transistors (MOSFETs), the fundamental and core component of microelectronic devices. The miniaturization of MOSFETs allowed for the integration of billions of transistors into a single microprocessor chip, and currently the industry is looking into the issues of fabricating MOSFETs to further scale down to a sub-10 nm node using three-dimensional features.

A significant challenge of fabricating MOSFETs at the sub-10 nm node is the patterning process, which requires excellent spatial uniformity, a detailed positioning of material, and perfect thickness control. To avoid the technical complexity and limitation of a conventional top-down patterning technique, lithography, a new approach of patterning MOSFET components should be developed.

In this work, selective deposition of molybdenum silicide (MoSix), molybdenum silicate (MoSiOx) and hafnium oxide (HfOx) were demonstrated using selective atomic layer deposition, a bottom-up approach of nanoscale patterning for MOSFETs. Selectivities were obtained by the difference in the chemical reactivity of precursors between the different substrates of interest. The deposition was performed in a self-limiting manner or carefully controlled decomposition of the precursor which provides conformality with a sub-nanoscale thickness control. In sum, this study focuses on the inherently selective deposition processes based on the surface chemistry and the engineering techniques for selectivity enhancements which can be integrated into three-dimensional MOSFET fabrication processes.

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