Advanced ESD Protection Using Graphene Technologies
One of the most pervasive reliability problems of the IC (integrated circuits) industry is the ESD (electrostatic discharging) induced. It causes up to 35% of total IC field failures and billions of dollars are lost annually. Therefore, on-chip ESD protection structures are commonly used to protect IC parts from being damaged by ESD stresses. And ESD protection design becomes one of the most challenging IC design problems.
The popular ESD protection structures may or may not be suitable for ESD protection at sub-32nm. ESD-protected I/O dummy monitor circuits can be used to evaluate ESD protection capability and suitability for general ICs. Various simple diode ESD protection structures is studied by mixed-mode ESD simulation and conducted comprehensive TLP (transmission line pulse) characterization for both individual ESD diodes and ESD-protected monitor circuit blocks. Stand-alone SCR and DTSCR are also studied to utilize the large current handling ability of SCR. TCAD simulation is discussed to provide design predictions. The goal is to provide practical design guidelines for robust ESD protection circuit design at 28nm node and beyond.
Compared to Si based ESD structures, 2D material graphene have unique electronic properties, it has been a rapidly rising star since it was found experimentally at 2004. Experimental results from transport measurements show that graphene has remarkably high electron mobility at room temperature. The structure of an electromechanical switch using graphene films is demonstrated. The graphene film is pulled into electrical contact with the bottom silicon by application of voltage bias between the layers. Contact is broken by mechanical restoring forces after bias is removed. The device switches several times without tearing. TLP testing confirmed that graphene is an attractive material for electromechanical switches which can be used as novel ESD protection structure.
Technology innovation is the key to IC design advances. However, conventional spiral inductors which have large size, poor Q-factor do not benefit from CMOS scaling. Novel IC inductors with vertical nano-particle magnetic cores could increase the L-density and thus reduce the area of the RF system-on-a-chip (SoC). A prototype LC-VCO using such a new magnetic-cored inductor is designed in an 180nm SOI CMOS.