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Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques


Energy minimization is one of the premiere design objectives in modern inte-

grated circuits (ICs). Currently, there is a pressing need to reduce energy con-

sumption in systems that span a wide array of form factors, ranging from mobile

phones/tablets, where simultaneously maximizing battery lifetime and satisfying

user experience is of paramount importance, to data centers/super-computers,

where even a small reduction in energy can translate to billions of dollars saved

in operating costs. However, as transistors continue to scale deeper into the sub-

micron regime, producing energy efficient designs has become more challenging.

Leakage power has increased significantly with respect to its total power con-

tribution, which in turn is exponentially dependent on operating temperature;

moreover, this is further exacerbated by increased device densities. Furthermore,

the impact of process variation in the design flow under these scenarios requires in-

creased attention, as small random alterations on a device (e.g., threshold-voltage

variations) can greatly impact overall energy and delay yields. Thus, as we con-

tinue to delve into the billion transistor era and beyond, new techniques are needed

to adapt to the continuously evolving physical landscape of IC technology.

This thesis presents several systematic and coordinated methods that simul-

taneously address energy and performance objectives for nano-scale technologies.

We introduce a multi-phase IC synthesis framework with an emphasis on opti-

mization parameters that, in recent years, have become more pronounced in near-

and super-threshold technology regimes; these parameters include gate switching

activity, input vector control, load capacitance, and operating temperature. We

present new gate-level and structural transformation techniques that, when per-

formed in a coordinated fashion, enable more energy efficient designs later in the

design flow. These techniques include gate sizing and threshold-voltage selection,

circuit unfolding, and re-timing. Each technique accounts for the aforementioned

parameters in generating ultra-low energy designs that satisfy the specified perfor-

mance target. We also present a scenario-based approach for optimization under

uncertainty in order to address the impact of process variation

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