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Toward a Generalized Model of Hardware Parallelism and Reconfigurability

  • Author(s): Black, Trevor
  • Advisor(s): Markovic, Dejan
  • et al.
Abstract

The end of Moore’s Law has created an increasing reliance on reconfiguration in the algorithm and in the hardware space to continue exponential speedup of application runtime. Increasingly exotic hardware designs such as GPUs, FPGAs, and Universal DSP devices are created with high levels of logical compute in mind, but necessitate increasingly complex control schemes to function as designed. This paper presents a unified mathematical model of Boolean computation for use in designing any reconfigurable or parallel hardware. Treating control signals as simple input signals, the bandwidth of a system’s controls determines how quickly the device can reconfigure. The maximum amount of computation, and the set of all problems that a device can be compute, can be cheaply deduced by the bandwidth and span of the control network.

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