Donald Bren School of Information and Computer Sciences

Chip synthesis deals with the transformation of a behavioral description into a fabricated chip. Typically, chip synthesis is carried out in three stages: behavioral, logic/sequential and layout synthesis. Since chip synthesis involves a multi-level synthesis task, integration and coordination of tasks for all levels of synthesis is the essential issue.

This dissertation addresses a chip synthesis paradigm and describes the key issues with regard to the integration of behavioral and layout synthesis for chip design. In order to successfully integrate all tasks in the chip synthesis process, a finite-state machine with a datapath (FSMD) design model and a sliced-layout architecture have been developed for chip synthesis. Using the sliced-layout architecture, a partitioning-based layout synthesis method and system have been developed to synthesize layout from generalized register-transfer (RT) netlists. In addition, based on the FSMD and the sliced-layout architecture, area and timing models are developed for behavioral synthesis. To incorporate layout information into behavioral synthesis, a unified representation is developed for behavioral synthesis. Using the unified representation and layout model, a layout-driven unit-binding approach is presented. Several sets of experiments were performed to validate the proposed approaches including the layout-synthesis method, the layout model and the layout-driven unit-binding task.