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Characterization, modeling and optimization of fills and stress in semiconductor integrated circuits


To improve manufacturability and yield, a number of fill structures are used in semiconductor manufacturing. These structures are CMP, active region (diffusion) and via fills. CMP (dummy) fills are used to reduce metal thickness variations due to chemical-mechanical polishing (CMP). Via fills are used to improve neighboring via printability, to improve mechanical stability of low-k dielectrics, and to reduce via resistance variability. Active region fills are used for STI CMP uniformity and threshold voltage variation reduction. Contact fills may be used for contact printability enhancement and contact resistance variability reduction. In this thesis, we additionally utilize via fills for reliability improvement of low-k and ultra low-k dielectrics, active region fills for stress optimization, and contact fills along with via fills for device temperature reduction. Although modern parasitic extraction tools accurately handle grounded fills and regular interconnects, such tools use only rough approximations to assess the capacitance impact of floating fills; these approximations include assuming that floating fills are grounded or that each fill is merged with neighboring ones. The accuracy of extractors must be improved without deviating from standard extraction flows. Furthermore, a thorough analysis of floating fill impact is needed by the industry to help select optimal fill shapes and pattern. In Chapter II, we show through 3D field solver simulations that the assumptions used in extractors result in significant inaccuracies. To reduce RC extractor inaccuracies, we provide a design of experiments (DOE) set for accurate extraction of coupling capacitances including interlayer coupling up to second neighboring layer. We provide a compact DOE structure from which multiple coupling capacitances can be obtained in one simulation to reduce the simulation time. We identify the relevant design and process parameters for fill analysis, and provide a thorough analysis of the floating fill impact on capacitances. Furthermore, we compare different fill algorithms and analyze how each parameter affects coupling. We provide this analysis methodology for designers to be able to analyze their own designs and BEOL process tuning. The final aspect of our contribution is a normalization-based integration methodology to improve RC extractor accuracy. We also extend our analyses and methodology to via fills and active region fills, which have more recently been introduced into semiconductor design-manufacturing methodologies and for which sufficient understanding is still lacking. Classical methods to insert fills focus on metal density uniformity, but do not take into consideration or are unable to minimize the impact of fills on circuit performance. Furthermore, interlayer impact due to fills is not considered during fill synthesis. Fill insertion guidelines exist [1] [2], but automation is needed to apply them for large designs. In Chapter III, we develop a novel fill insertion methodology, starting from a physical analogy, that heuristically minimizes coupling capacitance increase due to fill. Our methodology uses a grid model with bonds for energy minimization during fill insertion. We provide models for the bond energy network to map given fill insertion guidelines into an energy minimization problem. Our optimization methodology can automate the application of known fill insertion guidelines. We extend our methodology to enable critical net-aware and interlayer-aware fill optimization. Furthermore, we provide a power-aware fill methodology for power-critical circuits. Experiments show that the proposed optimization methods can reduce fill impact on coupling capacitances by up to 96.10% for 30% pattern density and up to 15.64% for 60% pattern density cases. We have observed total capacitance reductions in an industrial dual core product testcase with no degradation of topography uniformity, relative to traditional fills. Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source - shallow trench isolation (STI) - has not been fully utilized up to now for circuit performance improvement. Furthermore, the introduction of dual-stress liners (DSL) re- quires analyses and design guidelines for optimization. In Chapter IV, we present a new methodology that combines detailed placement and active-region fill insertion to exploit STI stress for performance improvement. We conduct process simulation of a production 65nm STI technology to develop mobility improvement models for STI width-mediated stress. We then utilize these models to perform STI stress-aware delay analysis of critical paths using a SPICE-based flow. We identify relevant layout parameters and automate the extraction process. We also achieve a timing-driven optimization of STI stress in standard cell designs, using detailed placement perturbation and active-region fill insertion to improve CMOS performance. We furthermore extend our optimization for intra-cell optimization. We assess the proposed analysis and optimization on small designs implemented with a 65nm production cell library and a standard synthesis, place and route flow. Our optimization improves clock frequency by 2.44% to 5.26% for inter-cell optimization and up to 11.32% for intra-cell STI width optimization. We also analyze DSL technology and provide design guidelines for layout optimization for DSL technology. The frequency improvement through exploitation of STI stress comes at practically zero cost in terms of design area and wirelength. CMP fills and via fills can furthermore alter the local mechanical stresses in the BEOL (back-end of the line), which can improve or degrade reliability. Designers require guidelines for fill insertion for reliability. We provide test structures to analyze the impact of fills on local mechanical stress using a generic 65nm BEOL process flow. Our test structures replicate common layout configurations in the presence of fills. In Chapter V, we conduct TCAD simulations on our test structures and also conduct a process sensitivity analysis. We tie the resultant stress to BEOL reliability concerns through identifying stress measurement locations. We show that the design of fills can reduce the nominal stress or stress gradients by up to 5x, theoretically providing significant improvement to BEOL reliability. We provide design guidelines for BEOL reliability improvement with fills. In particular, we assess whether via fills can be used for BEOL reliability improvement. We also show that connecting CMP fills to interconnects through via fills can improve BEOL reliability by more than 20%. Device heating is also an important issue particularly for SOI (silicon on insulator) technology. Local modifications of a layout with fills can alter device temperatures. It is possible to reduce the temperature in a transistor channel through proper layout design style and structures such as via fills and contact fills. In Chapter VI, we evaluate the impact of CMP, via and contact fills on temperature at the transistor level. We provide a TCAD-based analysis through the test structures we have designed. We provide design guidelines to reduce device temperature and hence the channel leakage. We show that device temperature can be reduced by connecting the device diffusion region or interconnects connected to the device to CMP fills through contact and via fills. We have shown that the proposed guidelines can reduce the temperature by 5oC with no penalty and device leakage up to and exceeding an order of magnitude if there is available area and performance flexibility to benefit the proposed guidelines

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