High-level library mapping for RT components
We present High-level library mapping (HLLM), a novel library mapping technique for RT level components that supports the current day design methodologies using High-level design and Design reuse. HLLM uses RT level functional behavior to perform mapping of a RT component onto another RT component of similar complexity. The technique is well-suited for mapping regularly-structured datapath and memory components. In this dissertation, we first introduce high-level library mapping and distinguish it from other library mapping approaches. Next, we define a generic library of reusable RT parts that provides the functional basis of HLLM. We demonstrate the HLLM approach on two classes of components, namely ALUs and memories. Our experimental results demonstrate the comprehensiveness and efficacy of the HLLM approach in mapping RT components. Finally, we describe the GENUS library environment and a user-interface to the HLLM system for performing RT level design. The HLLM approach we describe uses functional behavior to elevate library mapping from the logic to the RT level.