UCLA

The advent of next-generation sequencing has made a great impact on many applications from precision medicine to new drug discovery.

This motivates the research of FPGA acceleration for genome sequencing algorithms.

The recently developed quadratic-time SMEM seeding algorithm becomes a time-consuming computation kernel in genome sequencing, but it has not been well studied. The fundamental challenge of accelerating the SMEM algorithm is to handle its large volume of random memory accesses. While the state-of-the-art SMEM accelerator attempts to solve this by sacrificing the performance of individual processing elements to maximize the task-level parallelism, this design methodology suffers a serious resource underutilization issue. To resolve this issue, I propose SMEM++, a pipelined and time-multiplexed FPGA accelerator for the SMEM algorithm. SMEM++ adopts the canonical non-blocking pipeline methodology and implements a fully pipelined processing element design with the initiation interval equal to one.

Moreover, a communication interface adapter is designed to make the accelerator compatible to the designated FPGA platform interface and increase its portability.

The experiments on the Intel HARPv2 platform show that SMEM++ outperforms the original software by 24x, and outperforms the state-of-the-art SMEM accelerator design by 6.3x, even with 43% less logic resource consumption.