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Efficiency Improvement Techniques for Millimeter-Wave Transmitters


Strong demand for mm-wave high data-rate links in emerging 5G communication systems has resulted in substantial interest in mm-wave silicon (Si) based radio front-ends. The efficiency of the PA is a significant factor in the overall power dissipation and thermal management of mm-wave transceivers which have arrays with a large number of antennas (RF channels). This dissertation focused mainly on circuit design techniques for cm/mm-wave CMOS power amplifier efficiency improvement at frequencies from 15 GHz to 28 GHz. In addition, a DSP based solution is proposed to increase efficiency and performance of cellular (LTE band) transmitters in the 1-3 GHz frequency range.

For digital communication signals with multi-carrier modulation and high peak-to-average power ratios (PAPRs), high back-off efficiency of the PA is of significant importance. In the first part of the dissertation, possible implementations of linear and efficiency-enhanced CMOS PAs are described. The concept of stacking multiple FETs is applied in the design of symmetric and asymmetric Doherty power amplifiers, as well as compact linear PAs. The dissertation demonstrates that high power density can be achieved with PAs based on 4-stack power devices, while 2-stack devices can be designed to have exceptionally high efficiency due to lower losses. A two stage, high power Doherty PA that uses 4-stack devices in the final stages is demonstrated with more than 25 dBm output power and 25% back-off power added efficiency (PAE) at 6 dB back-off operating in the 15 GHz band. To minimize chip area, the Doherty combiner is based on an optimized, lumped element 90 degrees phase shifter. To overcome the inherent non-linear gain response of Doherty PAs and to minimize the complexity of digital pre-distortion (DPD) due to large channel bandwidth at mm-wave bands, a simple RF domain analog pre-distorter is demonstrated for the first time.

Various compact, linear 2-stack PAs are demonstrated based nMOS and pMOS FETs for saturated output powers in the range of 20 dBm in the Ka-band. Performance and reliability advantages of pMOS based PAs are shown. Also, by using inter-node impedance tuning with a shunt feedback drain-source capacitor, the PAE of the 2-stack PAs is increased even further, resulting in world record 46% PAE for the pMOS PA at 26.5 GHz.

Due to high passive losses in CMOS, achieving high efficiency Doherty PAs requires careful design and non-conventional synthesis methodology for the Doherty combiner. A high efficiency, symmetric Doherty PA for the Ka-band that is based on efficient 2-stack power devices and a low loss Doherty combiner synthesis technique is presented. At 6 dB back-off, the PAE exceeds 28% which corresponds to 1.4x higher PAE than achievable with ideal class B back-off from peak PAE. Such high efficiency is attained due to low combiner losses of 0.5 dB, which is less than half of what can be achieved with a conventional Doherty combiner. Furthermore, an asymmetric Doherty PA is reported that is based on low loss output Doherty combiner and uses a 2-stack cell in the main path and a 4-stack cell in the peaking path, thus improving efficiency at more than 6 dB back-off and achieving high output power. In addition, a compact modeling approach for large, parasitic-extracted PA transistors is presented, which considerably reduces simulation time and accelerates developments of CMOS PAs.

A typical time-division duplex (TDD) transmit/receive (T/R) mm-wave front-end comprises a power amplifier, a low noise amplifier (LNA), an antenna switch, and appropriate passive matching and combining networks. In this thesis, a synthesis methodology is proposed that minimizes the overall losses by combining the PA output and the LNA input matching networks together with the T/R switch into one network. The technique improves mm-wave transceiver performance in terms of PA efficiency and LNA noise figure (NF). The proposed T/R combiner can achieve high linearity and can handle large PA output voltage swings. The architecture can be implemented in any process which provides high integration capability. A Ka-band implementation is demonstrated in CMOS SOI that includes a high power, 4-stack based PA and an inductively source degenerated, cascode based LNA. Within the front-end, the PA achieves saturated output power of 23.6 dBm with peak PAE of 28%, while the LNA achieves NF of 3.2 dB.

Finally, in frequency division duplex (FDD) systems, spurious emissions from the transmitter (TX) can fall onto the receive (RX) band and lead to significant receiver desensitization. This dissertation proposes a DSP based solution that relies on a linear auxiliary receiver to cancel the RX band noise from the received signal. This technique allows reduction of duplexer rejection requirements in the RX band, and reduction of insertion loss in the TX band, thus, resulting in high PA efficiency and smaller duplexer footprint. PA architectures that inherently have high receive band noise (envelop tracking and digital PAs) can substantially benefit from this technique. More than 22 dB improvement in the signal to noise ratio (SNR) is shown without the presence of desired signal at the antenna.

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