Design of 60+Gb/s Serial-Link Transmitters Using Filter Techniques
The demand for off-chip data bandwidth of serial-link transceivers have been pushed beyond 40-Gb/s/link. With the potential aggregate data rate, power consumption and area must be reasonable. State-of-the-art serial-link transmitters operating at data rates beyond 40-Gb/s can contribute up to 40-45% power consumption while the FFE is limited to 2 taps. The main design challenge comes from the fact that producing output signal levels using large devices at high frequency is very power hungry. It is critical to low the power of transmitter at high data rate to enable high performance serial links.
This dissertation explores the potential of operating transmitters at data rates that approach the fundamental technology limit. Several circuit techniques are proposed to improve power efficiency and performance of serial-link transmitters. A LC-based feedforward equalizer (FFE) is proposed to eliminate the need of multiple MUXs. The design methodology of LC-ladder filter is proposed and applied to the FFE design to improve the bandwidth and the use of inductors. The serializer is power-optimized using a direct 4:1 multiplexer (MUX) at final stage with a novel 4:1 MUX design. An inverter-based digital-to-phase converter (DPC) using harmonic rejection filter is proposed to improve the phase linearity.
To verify the effectiveness of the proposed techniques, a 64-Gb/s transmitter prototype and an 8-bit DPC are designed and measured in 65-nm CMOS technology. The optimal use of on-chip inductors improve the bandwidth and power efficiency significantly. The proposed transmitter prototype, achieves a maximum data rate of 64.5 Gb/s and an energy efficiency of 3.1 fJ/b. The DPC demonstrates a maximum INL and DNL of 1.33 and 0.52 LSB while consumes a power of 4.3 mW at 1.5 GHz.