UCLA

Enabled by new storage mediums, Computation-in-Memory is a novel architecture that

has shown great potential in reducing the burden of massive data processing by bypassing

the communication and memory access bottleneck. Suggested by Cassuto and Crammer,

allowing for ultra-fast Hamming distance computations to be performed in resistive

memory with low-level conductance measurements has the potential to drastically speed up

many modern machine learning algorithms. Meanwhile, Hamming distance Computationin-

Memory remains a challenging task as a result of the non-negligible device variability

in practical resistive memory. In this thesis, as a follow-up to the work from Cassuto and

Crammer, we study memristor variability due to two distinct sources: resistance variation,

and the non-deterministic write process. First, we introduce a technique for estimating the

Hamming distance under resistance variation alone. Then, we propose error-detection and

error-correction schemes to deal with non-ideal write process. We then combine these results

to concurrently address both sources of memristor variabilities. In order to preserve

the low latency property of Computation-in-Memory, all of our approaches rely on only a

single vector-level conductance measurement. We use so-called inversion coding as a key

ingredient in our solutions and we prove the optimality of this code given the restrictions

on bit-accessible information. Lastly, we demonstrate the efficacy of our approaches on the

k-nearest neighbors classifier.