Minimization of memory traffic in high-level synthesis
In this paper we present a new transformation for the scheduling of memory accessing operations in High-Level Synthesis. This transformation is suited to memory-intensive applications with synthesized designs containing a secondary store accessed by explicit instructions. Such memory-intensive behaviors are commonly observed in video compression, image convolution, hydro-dynamics and mechatronics. Our transformation removes load instructions which become redundant during the transformation of loops. The advantage of this reduction is the decrease of secondary memory bandwidth demands. Our experiments on benchmarks from several application areas show that a significant reduction in the number of memory loads is obtainable.