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Design Enhancements And A Validation Framework For ARM Emulator

  • Author(s): Thota, Himabindu
  • Advisor(s): Renau, Jose
  • et al.
Abstract

Processor emulators allow micro-architecture researchers to evaluate research ideas quickly and at no extra cost. Micro-architecture Santa Cruz (MASC) Laboratory is developing an ARM processor emulator to execute ARM binaries. To ensure correctness of the emulator, it is expected that at the end of every instruction execution the modified registers, their contents, condition codes and any modified values in memory match that of the program execution on a computer with ARM processor. To this end, this work has three parts - first, to design and implement a validation infrastructure for the emulator ISA and the second, to improve the emulator functionality. Interestingly, these two goals go hand-in-hand. Having a validation infrastructure exposes incorrectly implemented or not yet implemented instructions while certain instructions prompt design enhancements in the validation infrastructure. Furthermore, we developed a methodology to generate Random Instruction Tests (RIT) to facilitate regression testing of the ARM emulator.

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