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Static timing analysis in VLSI design


The increasing complexity of digital designs and the requirement of timing measurements in various design stages make static timing analysis critical. Each design stage utilizes static timing analysis to evaluate the system performance, and then optimizes the design accordingly. An accurate and efficient timing analysis package is crucial for the success of the whole design process. We studied three important problems in static timing analysis: false paths, multi-cycle paths, and hierarchical timing analysis. Static timing analysis should deal with false paths and multi-cycle paths to produce accurate timings. Previous published works focused on dealing with false paths in static timing analysis. There are several approaches, such as labeling algorithm and node-splitting approach, using tags to label and eliminate false path timings. A large number of tags need to be created and propagated. Thus, the efficiency is deteriorated. For hierarchical timing analysis, timing analysis iteratively performed on flatten circuits suffers from low efficiency because of increasing design complexity. Inspired by the gap between challenges and current sub-optimal solutions, we proposed three new techniques: 1. A two-direction propagation is proposed which minimizes the number of tagged false path timings using a biclique covering approach. We proved that all the non-false paths are covered and all the false paths are removed. A polynomial heuristic to perform the biclique covering minimization in minimal degree order is also introduced. 2. A framework unified processing false paths and multi-cycle paths is proposed which expands the tag- based approach for false paths to cover multi-cycle paths. Following the biclique covering approach for false paths, we devise time shifting for multi-cycle paths to improve the efficiency. We prove that the unified framework produces accurate timings. 3. An abstract timing model reduction technique is proposed for hierarchical timing analysis. We introduce an iterative biclique-star replacement technique to minimize the abstract timing model, thus improving the efficiency. Combined the techniques proposed above, we provide an accurate and efficient static timing analysis package, which can be used in hierarchical design methodology

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