UC Santa Cruz

Translating the computation-critical part of an application to special-purpose hardware is a standard practice to achieve performance gain and speed-up in execution time. In this thesis, we chose a gene sequence aligner tool: Minimap2 as a workload. This thesis implements the kernel of Minimap2 in hardware using Verilog and parameterizes the design to support parallelism. We subsequently evaluate the design’s performance on timing, speed-up, and area utilization.