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Hardware Accelerator for Minimap-2 Kernel

Creative Commons 'BY' version 4.0 license

Translating the computation-critical part of an application to special-purpose hardware is a standard practice to achieve performance gain and speed-up in execution time. In this thesis, we chose a gene sequence aligner tool: Minimap2 as a workload. This thesis implements the kernel of Minimap2 in hardware using Verilog and parameterizes the design to support parallelism. We subsequently evaluate the design’s performance on timing, speed-up, and area utilization.

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