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Open Access Publications from the University of California

Analysis and Modeling of Large-Scale Variation on DACs and SRAMs

  • Author(s): Park, Henry Arnold
  • Advisor(s): Yang, Chih-Kong Ken
  • et al.

Evolution of CMOS circuits has been leveraged by continuous scaling of the feature size. Scaling has enabled integration of several billions of transistors in a single die with lower power consumption and throughput increase for the last two decades. However, the increasing process variability over die-to-die and within-die becomes an issue for the system reliability. The device model for the most advanced technology is becoming too complicated due to diverse physical effects arising from short channel length and high field, and makes it hard to rely on the model accuracy to precise estimate the productivity and reliability of a large-scale system. Therefore, the need to generate an accurate yield estimation model (or tool) based on the measurement data is required.

This work presents simple and fast reliability estimation techniques for two of the most widely used systems: digital-to-analog converter (DAC) and SRAM. The DAC is exclusively adopted by most mixed-signal systems such as high performance transceivers, digital phase-locked loop, clock-data recovery, and successive approximation. Depending on their purpose, the DAC design may demand different design targets. While many of the systematic performance degradations (especially dynamic linearity) can be handled by careful layout, circuit architecture, segmentation, and switching algorithm, the nonlinearity caused by unit element mismatch can only be handled by sizing up the device or by calibration. In any case, the achievable minimum nonlinearity should be

carefully considered from a yield estimation model. This model must be based on measurable mismatch information of the unit element, such as unit current in a currentsteering DAC, and it should be applicable to arbitrarily segmented structure. From the survey of existing models and their limitations, this work proposes two general models for the differential nonlinearity (DNL) and integral nonlinearity (INL) yield. The validity of the model is verified by measurement data from an 8-bit current-steering DAC fabricated in 90nm CMOS.

The second case study is for SRAM. Most microprocessors have various cache memories that are usually built by SRAM for its robust data retention and high access speed for both read and write. With the recent trend of multi-core processors in a single die in association with the decreasing feature size, the number of SRAM blocks and increasing density of the SRAM cell generate serious reliability issues. As an old tradition of SRAM design, the size of the cell is generally determined by yield from static stability margin or from dynamic perspectives that rely on the accuracy of the device model. Rapid yield estimation techniques such as importance sampling or response surface model present extreme cases, as their predictability of failure depends on the assumed variability of the few major parameters such as threshold level and mobility.

For better estimation of SRAM yield, built-in self-test (BIST) circuits are suggested in numerous publications that can improve the predictability of failure conditions. This failure condition is particularly useful for gauging time-dependent stability variation of the memory cell due to diverse effects such as NBTI and aging. The estimated failure condition found in BIST circuits can be used to counteract the failure mechanism to decrease the fail bit count such as controlling the cell supply. Such varying failure condition cannot be detected by traditional pass/fail based test. In addition, knowing the analog level of stability distribution greatly helps in reducing the power of the entire memory array by exploring the optimum lower supply level without failing read/write operation. Another particular utilization of the stability information is in correlation to the device model. SRAM designers face countless combinations of the device parameters to satisfy a specific stability margin. With large stability measurement data, their design

strategy can be more reliably verified.

However, none of the proposed techniques can be applied to a large memory array because of the speed issue and relatively incorrect estimation result. This work proposes a rapid yield estimation technique for discerning static stability. By using a small size onchip

ADC and direct bit-line access technique, the static read stability and write-ability of 6T SRAM cells are characterized. From the definitions of the new dynamic stability, the close correlation between the static estimation and the dynamic characteristics are demonstrated. The estimation results matched very well to the measured stability from a test chip in 65nm CMOS.

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