UC Santa Cruz
Design of a RISC-V Processor with OpenRAM Memories
- Author(s): Sowash, Jennifer Eve
- Advisor(s): Guthaus, Matthew R
- et al.
Memory compilers, such as OpenRAM, are an ideal addition to most digital chip designs as they automate netlist, layout, and characterization of memories. This thesis presents the first place & route of OpenRAM memories and adds write masking, which allows Open-RAM to generate the memories necessary for processor design. To perform synthesis and place & route, we modify OpenRAM’s timing and power model and physical model files. To add write masking, we alter OpenRAM’s netlist, layout, and characterization. These enhancements culminate in the place and route of a small RISC-V CPU with OpenRAM memories. This CPU is 2.14x smaller than the flip-flop implementation.