UC San Diego

Providing a reliable power distribution network (PDN) is a critical design challenge for mobile system on chip platforms. A well-designed power distribution network should be robust enough to support chipset performance while avoids eroding product profit margins through excessive design guardbanding. The solution space between these two requirements is small for PDN designs. On one hand, an inadequate PDN design can lead to test failures, missed performance targets, and intermittent functional problems in the field. On the other hand, some of the more direct PDN improvements such as adding on-die regulators, on-package discrete decoupling capacitors, and package layers increase die and package size, and could cost tens to hundreds of millions of dollars per product line. Mobile platform PDN design is challenging due to limited form factor, heterogeneous congested blocks with different design specifications, and adoption of multiple low-power techniques and modes. Therefore, it is important to develop a set of PDN design methodologies and analysis tools that can guide the product development from product inception through test and debug. This dissertation focuses on different aspects of reliable power distribution network design for mobile computing platforms. First, we propose an early-stage power distribution modeling framework to analyze the power distribution during design cycle. We consider the complete closed-loop system from voltage regulation module, printed circuit board, package and silicon die for the co- simulation. Subsequently, an enhanced time domain and frequency domain analysis flow is proposed. For assessing the performance of the power distribution in the presence of multiple functional power modes, we introduce a worst- case current loading generation. The current generation algorithm synthesizes the functional vector load based on anti-resonance (i.e., resonance-aware) and rogue wave to gain more realistic worst-case voltage variation. We investigate the impact of power distribution variation on the performance of mobile processors. We estimate the impact of power integrity considerations on low-power processor performance through pre-silicon simulation and post-silicon measurements. We present a predictive performance model under voltage and temperature variations to guide the designers in the early stages of design. As part of this effort, new emerging technologies for design of power distribution are investigated. A reliability- aware model for 3D stacked chips is developed. The model considers the complete system including Through Silicon Via (TSV), substrate noise and stacked dies from both time - and frequency-domain perspectives. Finally, we discuss the recent efficient direction towards on-die regulations for design and optimization of the Linear Dropout based PDN under worst performance. In summary, the complete framework of this thesis aims to provide the means for designing robust power distribution for current evolving mobile computing platforms