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Barrier Layers and Metal Fill for Back End of Line Processing


As semiconductor devices continue to scale down below the 10 nm node, deposition of conformal, ultra-thin layers on high aspect ratio features becomes very challenging. As such, there is a need to deposit these materials with precise thickness and stoichiometry control via atomic layer deposition (ALD). Two main applications for ALD occur during BEOL microelectronic device processing after the MOSFET has been fabricated: barrier layer deposition and interconnect fill. These two applications will be the focus of this dissertation. ALD barrier layers are typically conductive nitrides, as such, this work will discuss growing several nitrides with ALD using N2H4 which has the main advantage of being able to grow at lower deposition temperatures. Commonly used barrier layers, titanium nitride (TiN) and tantalum nitride (TaN) have been extensively studied in devices because of their ideal thermal, mechanical, and electrical properties and ability to act as metal diffusion barriers, but typically require high deposition temperatures due to using less reactive NH3 as the N-containing precursor. Additionally, amorphous boron nitride was explored due to it having shorter bonds than TiN and TaN potentially making it a more-effective diffusion barrier that could be scaled down to films that must be less than 5 nm thick. These three materials in particular will be the focus in Chapters 2 and 3.

Deposition of conductive interconnect metal in shrinking vias is another common problem facing the microelectronics industry. Traditionally, Al and then Cu have been used due to their high conductivities; however, in small critical dimensions, the resistivity of Cu increases due to electron scattering. Therefore, new materials and processing conditions are being explored that can offer lower resistivity for interconnect fill in these small critical dimension features. Chapter 4 of this dissertation will discuss two selective ALD processes (Co and Ru) that can allow for bottom-up fill of the interconnect metal. This would induce the formation and growth of larger grains, which are expected to decrease via and interconnect resistance. Reducing grain boundaries and decreasing surface roughness achieve this. For the analysis and characterization of ALD films, in situ XPS and STM along with ex situ AFM were mainly employed to characterize the chemical, electrical and topographical features of the deposited films and surfaces. To further study the conductivity of films, ex situ four-point probe measurements were performed.

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