UC San Diego

Networks-on-Chip (NoC) has been proposed as a scalable solution to the global communication challenges in nanoscale System-on-Chip designs. The use of NoCs with standardized interfaces facilitates the reuse of previously-designed and third-party-provided modules in new designs. Besides design and verification benefits, NoCs have also been advocated to address increasingly daunting clocking, signal integrity, and wire delay challenges. In this thesis, we present design methods for synthesizing NoC architectures that are optimized for specific applications. We first present a novel design flow that integrates floorplanning, NoC architecture synthesis, RTL generation, and detailed RTL design. The proposed design flow is very flexible in that it allows for different user-defined objectives and constraints. The proposed design flow also supports both unicast and multicast traffic. We then present two approaches to the NoC synthesis problem. The first approach is based on flow -set partitioning and Steiner-tree construction. In this approach, the problem is decomposed into the inter-related steps of finding a good flow-set partition, deriving a good physical network topology for each group using Steiner-tree-based algorithms, and providing an optimized implementation for the derived topologies. The second approach is based on a rip-up and re-route formulation that successively improves upon an intermediate solution by "ripping'' out a flow and freeing up any network resources occupied by it, then "re-routing'' the ripped-up flow over the remaining network. To consider multicast flows, the re-routing step is formulated as a minimum directed spanning tree problem. While both approaches are effective, we found that the rip-up and re-route approach is generally better. Therefore, we chose to extend this approach to consider two additional design dimensions. First, we describe extensions to consider 3D-NoC synthesis. This is motivated by the increasing viability of 3D integration that has opened new opportunities for chip design innovations. To support 3D-NoC synthesis, we propose accurate power and delay models for 3D-wires with through-silicon-vias. Second, we describe extensions to support multiple traffic profiles, which are useful for design applications that support multiple usage scenarios, each with its own traffic profile. Finally, all proposed algorithms have been integrated into a software package called ARIES.